some improvements
This commit is contained in:
parent
a53abe0ff9
commit
c46379c117
@ -1,4 +1,4 @@
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VHDL_PKG += src/cpupkg.vhd
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VHDL_TB += src/TBRechner.vhd
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VHDL_SRC += src/RegFile.vhd src/CPU.vhd src/MemInterface.vhd src/antibeat_device.vhd src/FetchDecode.vhd src/ALU.vhd src/RAM.vhd
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VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd src/Rechner.vhd
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VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd src/MemGuard.vhd src/MMIO_Uart.vhd src/clkDivider.vhd src/ClkEnable.vhd src/MemoryMapper.vhd
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14
UCF/xc5vlx110t-3-ff1136.ucf
Normal file
14
UCF/xc5vlx110t-3-ff1136.ucf
Normal file
@ -0,0 +1,14 @@
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NET idRS232 LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI
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NET odRS232 LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI
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NET reset LOC="E9";
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NET ic200MhzClk LOC = L19 | IOSTANDARD = LVTTL; #200Mhz Clk
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NET clk LOC = "AH15"; #100Mhz clk
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NET data_print_2(0) LOC="AE24" | IOSTANDARD = SSTL18_II_DCI;
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NET data_print_2(1) LOC="AD24" | IOSTANDARD = SSTL18_II_DCI;
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NET data_print_2(2) LOC="AD25" | IOSTANDARD = SSTL18_II_DCI;
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NET data_print_2(3) LOC="G16" | IOSTANDARD = LVTTL;
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NET data_print_2(4) LOC="AD26" | IOSTANDARD = SSTL18_II_DCI;
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NET data_print_2(5) LOC="G15" | IOSTANDARD = LVTTL;
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NET data_print_2(6) LOC="L18" | IOSTANDARD = LVTTL;
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NET data_print_2(7) LOC="H18" | IOSTANDARD = LVTTL;
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6
asm/bootloader.s
Normal file
6
asm/bootloader.s
Normal file
@ -0,0 +1,6 @@
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start:
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43
asm/test-jmc.s
Normal file
43
asm/test-jmc.s
Normal file
@ -0,0 +1,43 @@
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start:
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lui $0, 0
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lui $1, 35
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lui $2, 36
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jmc print
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sto $1, 65521
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jmc print
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jmp end
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print:
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add $30, $31, $0
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sto $30, 65521
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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sto $30, 65521
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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sto $30, 65521
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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shr $30, $30, $0
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sto $30, 65521
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sto $1, 65521
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ret
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sto $2, 65521
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end:
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hlt
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60
asm/test-read-uart.s
Normal file
60
asm/test-read-uart.s
Normal file
@ -0,0 +1,60 @@
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start:
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loa $1, 65520
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jmc print
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jmc wait
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jmp start
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print:
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add $20, $1, $0
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sto $20, 65521
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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sto $20, 65521
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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sto $20, 65521
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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shr $20, $20, $0
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sto $20, 65521
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ret
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wait:
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lui $10, 600
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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shl $10, $10, $0
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lui $11, 1
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loop:
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sub $10, $10, $11
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jpz endloop
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jmp loop
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endloop:
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ret
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7
asm/uart-test.s
Normal file
7
asm/uart-test.s
Normal file
@ -0,0 +1,7 @@
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start:
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lui $1, 71
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loop:
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sto $1, 65521
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jmp loop
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hlt
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@ -6,7 +6,7 @@
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my $nr_instr_bytes = 4;
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my $nr_opcode_bits = 6;
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my $nr_reg_bits = 5;
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my $startaddr = 0;
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my $startaddr = -1;
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# mnemonnic to opcode conversion
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my %opcodes = (
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@ -26,6 +26,8 @@ my %opcodes = (
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'jpc' => 0x0D,
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'jmp' => 0x0E,
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'lui' => 0x0F,
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'jmc' => 0x10,
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'ret' => 0x11,
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'hlt' => 0x3F
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);
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@ -304,6 +306,14 @@ while ( my $line = <$src> ) {
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elsif ( $INSTR eq "jpc" ) {
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$label = $REST;
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}
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elsif ( $INSTR eq "jmc" ) {
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$label = $REST;
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my $dst = 31;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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}
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elsif ( $INSTR eq "jmp" ) {
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$label = $REST;
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}
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@ -326,6 +336,12 @@ while ( my $line = <$src> ) {
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;
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}
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}
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elsif ( $INSTR eq "ret" ) {
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my $op1=31;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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}
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elsif ( $INSTR =~ /^(.*):$/ ) {
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$labels{$1} = $addr;
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$addr--;
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@ -345,7 +361,10 @@ while ( my $line = <$src> ) {
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$instruction->{opc} = $opc;
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$instruction->{comment} = $line;
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$instruction->{label} = $label;
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if ($line =~/jmc/) {
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print "-" .$instruction->{label}."-\n";
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}
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push( @instructions, $instruction );
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}
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@ -53,7 +53,7 @@ begin
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sdOp1 <= '0' & idOperand1;
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sdOp2 <= '0' & idOperand2;
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process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate)
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process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate, idOperand1)
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begin
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if (icOperation = shl) then
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sdTempResult <= sdOp1(31 downto 0) & "0";
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@ -65,7 +65,7 @@ begin
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sdTempResult <= (others => '-');
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elsif (icOperation = loa) then
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sdTempResult <= sdOp2;
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sdTempResult <= '0' & idImmidiate;
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elsif (icOperation = li) then
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sdTempResult <= '0' & idImmidiate;
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elsif (icOperation = add) then
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45
src/CPU.vhd
45
src/CPU.vhd
@ -57,7 +57,10 @@ architecture Behavioral of CPU is
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ocLoadInstr : out std_logic; --! load instruction control signal
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ocNextPC : out std_logic; --! increment pc
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ocAddrSel : out std_logic; --! pc on addressbus
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ocJump : out std_logic --! do a ocJump
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ocJump : out std_logic; --! do a ocJump
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ocPCregister : out std_logic; --! put PC to register File
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ocUsePC : out std_logic; --! use Register to fill in the PC
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ocLoad : out std_logic --! put databus to ALU immediate port
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);
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end component;
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@ -71,6 +74,8 @@ architecture Behavioral of CPU is
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odRegA : out DATA;
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odRegB : out DATA;
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icPC : in std_logic; -- select PC as input to RegisterFile
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idPC : in DATA;
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icRegINsel : in std_logic_vector(4 downto 0);
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@ -110,6 +115,9 @@ architecture Behavioral of CPU is
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icLoadInstr : in std_logic;
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icJump : in std_logic;
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icNextPC : in std_logic;
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idPC : in ADDRESS;
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icUsePC : in std_logic;
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odPC : out ADDRESS;
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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@ -134,7 +142,16 @@ architecture Behavioral of CPU is
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idAddressCPU : in ADDRESS
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);
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end component;
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signal sdPC : DATA;
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signal scPCregister : std_logic;
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signal scUsePC : std_logic;
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signal sdPCfetch : ADDRESS;
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signal scLoad : std_logic;
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signal scOpCode : optype;
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signal sdCarryRF : std_logic;
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signal sdZeroRF : std_logic;
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@ -148,10 +165,10 @@ architecture Behavioral of CPU is
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signal sdAkkuRes : DATA;
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signal sdCarryAkku : std_logic;
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signal sdZeroAkku : std_logic;
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signal sdDataOut : DATA;
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signal sdDataIn : DATA;
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signal sdAddress : ADDRESS;
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signal sdImmidiate : DATA;
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signal sdImmidiateALU: DATA;
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signal sdRegAsel : std_logic_vector(4 downto 0);
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signal sdRegBsel : std_logic_vector(4 downto 0);
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signal sdRegINsel : std_logic_vector(4 downto 0);
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@ -172,7 +189,10 @@ begin
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ocLoadInstr => scLoadInstr,
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ocNextPC => scNextPC,
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ocAddrSel => scAddrSel,
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ocJump => scJump
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ocJump => scJump,
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ocPCregister => scPCregister,
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ocUsePC => scUsePC,
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ocLoad => scLoad
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);
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RF: RegFile PORT MAP(
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@ -183,6 +203,9 @@ begin
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icRegBsel => sdRegBsel,
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icRegINsel => sdRegINsel,
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icPC => scPCregister,
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idPC => sdPC,
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idDataIn => sdAkkuRes,
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idCarryIn => sdCarryAkku,
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idZeroIn => sdZeroAkku,
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@ -198,7 +221,7 @@ begin
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Calc : ALU Port MAP(
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idOperand1 => sdRegA,
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idOperand2 => sdRegB,
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idImmidiate => sdImmidiate,
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idImmidiate => sdImmidiateALU,
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idCarryIn => sdCarryRF,
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odResult => sdAkkuRes,
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@ -208,6 +231,8 @@ begin
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icOperation => scOpCode
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);
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sdPC(31 downto 16) <= (others=>'0');
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FaD : FetchDecode PORT MAP(
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iClk => iClk,
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iReset => iReset,
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@ -216,8 +241,11 @@ begin
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icAddrSel => scAddrSel,
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icLoadInstr => scLoadInstr,
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icJump => scJump,
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icNextPC => scNextPC,
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icNextPC => scNextPC,
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odPC => sdPC(15 downto 0),
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idPC => sdRegA(15 downto 0),
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icUsePC => scUsePC,
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odAddress => sdAddress,
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odImmidiate => sdImmidiate,
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odRegAsel => sdRegAsel,
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@ -239,6 +267,9 @@ begin
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idAddressCPU => sdAddress
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);
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sdImmidiateALU <= bdData when scLoad='1' else
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sdImmidiate;
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end Behavioral;
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64
src/ClkEnable.vhd
Normal file
64
src/ClkEnable.vhd
Normal file
@ -0,0 +1,64 @@
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--------------------------------------------------------------------------------
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-- Entity: ClkEnable
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--------------------------------------------------------------------------------
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-- Copyright ... 2011
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-- Filename : ClkEnable.vhd
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-- Creation date : 2012-04-06
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-- Author(s) : marcel eckert (eckert@hsu-hh.de)
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--------------------------------------------------------------------------------
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--! @file
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--! @brief Implements a generic ClkEnable generator
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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--! brief Implements a generic ClkEnable generator
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--! detailed Implements a generic ClkEnable generator. Based on an input frequency
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--! <GEN_FreqIn_Hz>, an output enable (1 <GEN_FreqIn_Hz> period) is generated every
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--! <GEN_FreqOut_Hz> periods
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entity clkEnable is
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generic(
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GEN_FreqIn_Hz : integer := 200000000; --! signal description input clock frequency in Hz for <iClkIn>
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GEN_FreqOut_Hz : integer := 100000000 --! signal description output clock frequency in Hz for <oClkEn>
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);
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port (
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iClkin : in STD_LOGIC; --! signal description input clock
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iReset : in STD_LOGIC; --! signal description synchronous reset (should be tied to '0')
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oeClkEn : out STD_LOGIC --! signal description output clockEnable
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);
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end clkEnable;
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architecture Behavioral of clkEnable is
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constant cLimit : integer := GEN_FreqIn_Hz / GEN_FreqOut_Hz;
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signal sCounter : integer range 0 to (cLimit-1) := 0;
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signal seClkEn : STD_LOGIC := '1';
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begin
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process (iClkIn)
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begin
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if (rising_edge(iClkIn)) then
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if (iReset = '1') then
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sCounter <= 0;
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seClkEn <= '1';
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elsif (sCounter = (cLimit-1)) then
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sCounter <= 0;
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seClkEn <= '1';
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else
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sCounter <= sCounter + 1;
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seClkEn <= '0';
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end if;
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end if;
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end process;
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oeClkEn <= seClkEn;
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end Behavioral;
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|
@ -42,8 +42,10 @@ entity FetchDecode is
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icAddrSel : in std_logic;
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icLoadInstr : in std_logic;
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icJump : in std_logic;
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icNextPC : in std_logic;
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icNextPC : in std_logic;
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odPC : out ADDRESS;
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idPC : in ADDRESS;
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icUsePC : in std_logic;
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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odRegAsel : out std_logic_vector(4 downto 0);
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@ -66,7 +68,7 @@ architecture Behavioral of FetchDecode is
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signal scOp, scOp_next : OPTYPE;
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begin
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Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp, sdRegAsel, sdRegBsel, sdRegINsel)
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Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp, sdRegAsel, sdRegBsel, sdRegINsel, icUsePC, idPC)
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begin
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-- defaults
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sdAdr_next <= sdAdr;
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@ -80,7 +82,7 @@ begin
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--! ISA Definition
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if (icLoadInstr = '1') then
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sdAdr_next <= "0000" & idData(11 downto 0);
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sdAdr_next <= idData(15 downto 0);
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sdImmidiate_next <= "0000000000000000" & idData(15 downto 0);
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sdRegINsel_next <= idData(25 downto 21);
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sdRegAsel_next <= idData(20 downto 16);
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@ -102,11 +104,17 @@ begin
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when "001100" => scOp_next <= jpz;
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when "001101" => scOp_next <= jpc;
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when "001110" => scOp_next <= jmp;
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when "001111" => scOP_next <= li;
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when "001111" => scOP_next <= li;
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when "010000" => scOp_next <= jmc;
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when "010001" => scOp_next <= ret;
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when others => scOp_next <= hlt;
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end case;
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end if;
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if (icUsePC = '1') then
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sdPC_next <= idPC;
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||||
end if;
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||||
|
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if (icJump = '1') then
|
||||
sdPC_next <= sdAdr;
|
||||
|
||||
@ -114,8 +122,9 @@ begin
|
||||
|
||||
if (icNextPC = '1') then
|
||||
sdPC_next <= sdPC + '1';
|
||||
|
||||
end if;
|
||||
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
@ -145,9 +154,12 @@ begin
|
||||
end process;
|
||||
|
||||
-- Output
|
||||
odAddress <= sdAdr when icAddrSel = '0' and icLoadInstr = '0' else
|
||||
sdAdr_next when icAddrSel = '0' and icLoadInstr = '1' else
|
||||
sdPC; -- addr_sel = '1'
|
||||
odAddress <= idPC when icUsePC = '1' else
|
||||
sdAdr when icAddrSel = '0' and icLoadInstr = '0' else
|
||||
sdAdr_next when icAddrSel = '0' and icLoadInstr = '1' else
|
||||
sdPC; -- addr_sel = '1'
|
||||
|
||||
odPC <= sdPC;
|
||||
|
||||
ocOperation <= scOp when icLoadInstr = '0' else
|
||||
scOp_next;
|
||||
|
283
src/MMIO_Uart.vhd
Normal file
283
src/MMIO_Uart.vhd
Normal file
@ -0,0 +1,283 @@
|
||||
-------------------------------------------------------
|
||||
--! @file
|
||||
--! @brief <short description>
|
||||
--! @author Dominik Meyer
|
||||
--! @email dmeyer@hsu-hh.de
|
||||
--! @date 2013-07-18
|
||||
-------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.cpupkg.all;
|
||||
|
||||
entity MMIO_Uart is
|
||||
generic (
|
||||
GEN_start : std_logic_vector(15 downto 0) := x"FFF0";
|
||||
GEN_SysClockinHz : integer := 100000000;
|
||||
GEN_Baudrate : integer := 57600;
|
||||
GEN_HasExternBaudLimit : boolean := true
|
||||
);
|
||||
port (
|
||||
|
||||
odRS232 : out std_logic;
|
||||
idRS232 : in std_logic;
|
||||
|
||||
ocInterrupt : out std_logic; --! high if data is available
|
||||
|
||||
odDebug : out std_logic_vector(7 downto 0);
|
||||
|
||||
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA; --! connection to databus
|
||||
idAddress : in ADDRESS; --! connection to addressbus
|
||||
icEnable : in std_logic; --! enable or disable RAM
|
||||
icRnotW : in std_logic --! read/write control
|
||||
);
|
||||
end MMIO_Uart;
|
||||
|
||||
architecture arch of MMIO_Uart is
|
||||
|
||||
component UART
|
||||
generic (
|
||||
GEN_SysClockinHz : integer;
|
||||
GEN_Baudrate : integer;
|
||||
GEN_HasExternBaudLimit : boolean
|
||||
);
|
||||
port (
|
||||
iSysClk : in std_logic;
|
||||
ieClkEn : in std_logic;
|
||||
iReset : in std_logic;
|
||||
icBaudLExt : in integer;
|
||||
icSend : in std_logic;
|
||||
idDataSend : in std_logic_vector ( 7 downto 0 );
|
||||
ocSEmpty : out std_logic;
|
||||
ocSFull : out std_logic;
|
||||
ocSAlmostE : out std_logic;
|
||||
ocSAlmostF : out std_logic;
|
||||
odTransmit : out std_logic;
|
||||
odDataRcvd : out std_logic_vector ( 7 downto 0 );
|
||||
ocREmpty : out std_logic;
|
||||
ocRFull : out std_logic;
|
||||
ocRAlmostE : out std_logic;
|
||||
ocRAlmostF : out std_logic;
|
||||
icRReadEn : in std_logic;
|
||||
idReceive : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
signal srTransmit : std_logic_vector(31 downto 0);
|
||||
signal srReceive : std_logic_vector(31 downto 0);
|
||||
signal srStatus : std_logic_vector(31 downto 0);
|
||||
signal srBaud : std_logic_vector(31 downto 0);
|
||||
signal scBaud : integer;
|
||||
|
||||
|
||||
signal tData : DATA;
|
||||
|
||||
--
|
||||
-- UART
|
||||
--
|
||||
signal scUARTsend, scUartReadEnable : std_logic;
|
||||
signal scUARTSempty, scUARTSfull : std_logic;
|
||||
signal scUARTSalmostE, scUARTSalmostF : std_logic;
|
||||
signal scUARTRempty, scUARTRfull : std_logic;
|
||||
signal scUARTRalmostE, scUARTRalmostF : std_logic;
|
||||
|
||||
|
||||
--
|
||||
-- FSM
|
||||
--
|
||||
type states is (st_start, st_idle, st_read, st_write);
|
||||
signal current_state : states;
|
||||
|
||||
begin
|
||||
|
||||
scBaud <= to_integer(unsigned(srBaud));
|
||||
|
||||
odDebug <= srTransmit(7 downto 0);
|
||||
|
||||
uart0: UART
|
||||
generic map(
|
||||
GEN_SysClockinHz => GEN_SysClockinHz,
|
||||
GEN_Baudrate => GEN_Baudrate,
|
||||
GEN_HasExternBaudLimit => GEN_HasExternBaudLimit
|
||||
)
|
||||
port map(
|
||||
iSysClk => iClk,
|
||||
ieClkEn => '1',
|
||||
iReset => iReset,
|
||||
icBaudLExt => scBaud,
|
||||
icSend => scUARTsend,
|
||||
idDataSend => srTransmit(7 downto 0),
|
||||
ocSEmpty => scUARTSempty,
|
||||
ocSFull => scUARTSfull,
|
||||
ocSAlmostE => scUARTSalmostE,
|
||||
ocSAlmostF => scUARTSalmostF,
|
||||
odTransmit => odRS232,
|
||||
odDataRcvd => srReceive(7 downto 0),
|
||||
ocREmpty => scUARTRempty,
|
||||
ocRFull => scUARTRfull,
|
||||
ocRAlmostE => scUARTRalmostE,
|
||||
ocRAlmostF => scUARTRalmostF,
|
||||
icRReadEn => scUartReadEnable,
|
||||
idReceive => idRS232
|
||||
);
|
||||
|
||||
srStatus <= scUARTRempty & scUARTRfull & scUARTRalmostE & scUARTRalmostF & scUARTSempty & scUARTSfull & scUARTSalmostE & scUARTSalmostF & x"000000";
|
||||
|
||||
ocInterrupt <= not scUARTRempty;
|
||||
|
||||
process(iClk, iReset)
|
||||
begin
|
||||
if (iReset = '1') then
|
||||
srBaud <= (others=>'0');
|
||||
srTransmit <= x"00000000";
|
||||
srReceive(30 downto 8) <= (others=>'0');
|
||||
|
||||
current_state <= st_start;
|
||||
|
||||
elsif (rising_edge(iClk)) then
|
||||
case current_state is
|
||||
when st_start =>
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
current_state <= st_idle;
|
||||
when st_idle =>
|
||||
if (icEnable = '1' and idAddress >= GEN_start and idAddress <= GEN_start + 2) then
|
||||
|
||||
-- Status Register
|
||||
if (idAddress = GEN_start) then
|
||||
if (icRnotW = '0') then
|
||||
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
|
||||
current_state <= st_write;
|
||||
|
||||
else
|
||||
tData <= srStatus;
|
||||
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
|
||||
current_state <= st_read;
|
||||
end if;
|
||||
-- Transmit Register
|
||||
elsif(idAddress = GEN_start+1) then
|
||||
if (icRnotW = '0') then
|
||||
srTransmit <= bdData;
|
||||
|
||||
scUARTsend <= '1';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
|
||||
current_state <= st_write;
|
||||
|
||||
else
|
||||
tData <= (others=>'0');
|
||||
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
|
||||
current_state <= st_read;
|
||||
end if;
|
||||
|
||||
-- receive Register
|
||||
elsif(idAddress = GEN_start+2) then
|
||||
if (icRnotW = '0') then
|
||||
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
|
||||
current_state <= st_write;
|
||||
|
||||
else
|
||||
tData <= srReceive;
|
||||
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '1';
|
||||
|
||||
|
||||
current_state <= st_read;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
current_state <= st_idle;
|
||||
end if;
|
||||
when st_read =>
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
current_state <= st_idle;
|
||||
|
||||
when st_write =>
|
||||
scUARTsend <= '0';
|
||||
scUartReadEnable <= '0';
|
||||
|
||||
current_state <= st_idle;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
bdData <= srStatus when icRnotW = '1' and idAddress=GEN_start else
|
||||
srReceive when icRnotW = '1' and idAddress=GEN_start+2 else
|
||||
(others => 'Z');
|
||||
|
||||
end arch;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
46
src/MemGuard.vhd
Normal file
46
src/MemGuard.vhd
Normal file
@ -0,0 +1,46 @@
|
||||
-------------------------------------------------------
|
||||
--! @file
|
||||
--! @brief memory guard to only answer for the correct memory space
|
||||
--! @author Dominik Meyer
|
||||
--! @email dmeyer@hsu-hh.de
|
||||
--! @date 2013-07-18
|
||||
-------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
--! memory guard to only answer for the correct memory space
|
||||
|
||||
entity MemGuard is
|
||||
generic (
|
||||
GEN_start : std_logic_vector(15 downto 0) := x"0000";
|
||||
GEN_end : std_logic_vector(15 downto 0) := x"0004"
|
||||
|
||||
);
|
||||
|
||||
port (
|
||||
icAddr : in std_logic_vector(15 downto 0);
|
||||
ocEnable : out std_logic
|
||||
|
||||
);
|
||||
end MemGuard;
|
||||
|
||||
architecture arch of MemGuard is
|
||||
|
||||
begin
|
||||
|
||||
|
||||
process(icAddr)
|
||||
begin
|
||||
if (icAddr >= GEN_start and icAddr <= GEN_end) then
|
||||
ocEnable <= '1';
|
||||
else
|
||||
ocEnable <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arch;
|
||||
|
54
src/MemoryMapper.vhd
Normal file
54
src/MemoryMapper.vhd
Normal file
@ -0,0 +1,54 @@
|
||||
-------------------------------------------------------
|
||||
--! @file
|
||||
--! @brief Maps memory devices to a given memory space
|
||||
--! @author Dominik Meyer
|
||||
--! @email dmeyer@hsu-hh.de
|
||||
--! @date 2010-06-03
|
||||
-------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
|
||||
--! Maps memory devices to a given memory space
|
||||
entity MemoryMapper is
|
||||
port(
|
||||
start : in std_logic_vector(15 downto 0); --! start of memory space
|
||||
stop : in std_logic_vector(15 downto 0); --! end of mempry space
|
||||
|
||||
adr_in : in std_logic_vector(15 downto 0);
|
||||
|
||||
req_in : in std_logic; --! ram request type
|
||||
req_out : out std_logic; --! ram request type
|
||||
|
||||
enable : out std_logic;
|
||||
|
||||
adr_out : out std_logic_vector(15 downto 0)
|
||||
|
||||
);
|
||||
end MemoryMapper;
|
||||
|
||||
|
||||
--! architecture to map memory devices to memory space
|
||||
architecture arch of MemoryMapper is
|
||||
|
||||
begin
|
||||
|
||||
process(adr_in, req_in, start, stop)
|
||||
begin
|
||||
|
||||
if (adr_in >= start and adr_in <= stop) then
|
||||
req_out <= req_in;
|
||||
adr_out <= adr_in-start;
|
||||
enable <= '1';
|
||||
else
|
||||
req_out <= '0';
|
||||
enable <= '0';
|
||||
adr_out <= (others => 'Z');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arch;
|
||||
|
80
src/RAM.vhd
80
src/RAM.vhd
@ -34,17 +34,61 @@ architecture arch of RAM is
|
||||
type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
|
||||
|
||||
constant Prog1 : MEMORY := ( --! 4k * 32bit of RAM
|
||||
1 => B"00111100001000000000000000000101", --lui $1, 5
|
||||
2 => B"00111100010000000000000000000110", --lui $2, 6
|
||||
3 => B"00111100011000000000000000000000", --lui $3, 0
|
||||
4 => B"00111100100000000000000000000001", --lui $4, 1
|
||||
5 => B"00010000101000000001000000000000", --add $5, $0, $2
|
||||
6 => B"00010000011000110000100000000000", --add $3, $3, $1
|
||||
7 => B"00010100101001010010000000000000", --sub $5, $5, $4
|
||||
8 => B"00110000000000000000000000001010", --jpz end
|
||||
9 => B"00111000000000000000000000000110", --jmp loop
|
||||
10 => B"11111100000000000000000000000000", --hlt
|
||||
|
||||
0 => B"00001100001000001111111111110000", --loa $1, 65520
|
||||
1 => B"01000011111000000000000000000100", --jmc print
|
||||
2 => B"01000011111000000000000000100010", --jmc wait
|
||||
3 => B"00111000000000000000000000000000", --jmp start
|
||||
4 => B"00010010100000010000000000000000", --add $20, $1, $0
|
||||
5 => B"00001000000101001111111111110001", --sto $20, 65521
|
||||
6 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
7 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
8 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
9 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
10 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
11 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
12 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
13 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
14 => B"00001000000101001111111111110001", --sto $20, 65521
|
||||
15 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
16 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
17 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
18 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
19 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
20 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
21 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
22 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
23 => B"00001000000101001111111111110001", --sto $20, 65521
|
||||
24 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
25 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
26 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
27 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
28 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
29 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
30 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
31 => B"00000110100101000000000000000000", --shr $20, $20, $0
|
||||
32 => B"00001000000101001111111111110001", --sto $20, 65521
|
||||
33 => B"01000100000111110000000000000000", --ret
|
||||
34 => B"00111101010000000000001001011000", --lui $10, 600
|
||||
35 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
36 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
37 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
38 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
39 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
40 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
41 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
42 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
43 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
44 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
45 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
46 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
47 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
48 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
49 => B"00000001010010100000000000000000", --shl $10, $10, $0
|
||||
50 => B"00111101011000000000000000000001", --lui $11, 1
|
||||
51 => B"00010101010010100101100000000000", --sub $10, $10, $11
|
||||
52 => B"00110000000000000000000000110110", --jpz endloop
|
||||
53 => B"00111000000000000000000000110011", --jmp loop
|
||||
54 => B"01000100000111110000000000000000", --ret
|
||||
|
||||
|
||||
others => (others => '0')
|
||||
@ -67,17 +111,19 @@ begin
|
||||
tData <= (others => '0');
|
||||
|
||||
elsif (rising_edge(iClk)) then
|
||||
if (icRnotW = '0' and icEnable = '1') then
|
||||
sRam(conv_integer(unsigned(idAddress))) <= bdData;
|
||||
else
|
||||
tData <= sRam(conv_integer(unsigned(idAddress)));
|
||||
end if;
|
||||
if (icEnable = '1') then
|
||||
if (icRnotW = '0') then
|
||||
sRam(conv_integer(unsigned(idAddress))) <= bdData;
|
||||
else
|
||||
tData <= sRam(conv_integer(unsigned(idAddress)));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
bdData <= tData when icRnotW = '1' else
|
||||
bdData <= tData when icRnotW = '1' and icEnable='1' else
|
||||
(others => 'Z');
|
||||
|
||||
end arch;
|
||||
|
@ -1,68 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library work;
|
||||
use work.cpupkg.all;
|
||||
|
||||
entity Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
|
||||
port( clk : in std_logic; -- Taktsignal
|
||||
reset : in std_logic; -- Resetsignal
|
||||
data_print_1: out DATA;
|
||||
data_print_2: out DATA
|
||||
);
|
||||
end Rechner;
|
||||
|
||||
architecture Struktur of Rechner is
|
||||
|
||||
signal DATAbus : std_logic_vector(31 downto 0); -- DATAbus
|
||||
signal address : std_logic_vector(15 downto 0); -- Adressbus
|
||||
signal rw_ram : std_logic; -- read/write-Signal RAM
|
||||
signal enable : std_logic;
|
||||
|
||||
component CPU is
|
||||
Port(
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA; --! connection to databus
|
||||
odAddress : out std_logic_vector(15 downto 0); --! connection to addressbus
|
||||
ocEnable : out std_logic; --! enable or disable RAM
|
||||
ocRnotW : out std_logic --! read/write control
|
||||
);
|
||||
end component;
|
||||
|
||||
component RAM is
|
||||
port (
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA; --! connection to databus
|
||||
idAddress : in std_logic_vector(15 downto 0); --! connection to addressbus
|
||||
icEnable : in std_logic; --! enable or disable RAM
|
||||
icRnotW : in std_logic --! read/write control
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
CPU_1: CPU port map(
|
||||
iClk => clk,
|
||||
iReset => reset,
|
||||
bdData => DATAbus,
|
||||
odAddress => address,
|
||||
ocEnable => enable,
|
||||
ocRnotW => rw_ram);
|
||||
|
||||
RAM_1: RAM port map(
|
||||
iClk => clk,
|
||||
iReset => reset,
|
||||
bdData => DATAbus,
|
||||
idAddress => address,
|
||||
icEnable => enable,
|
||||
icRnotW => rw_ram);
|
||||
|
||||
data_print_1 <= DATAbus; -- Ausgabe des DATAbus auf dem LCD-Display
|
||||
data_print_2 <= "0000000000000000" & address;
|
||||
|
||||
end Struktur;
|
@ -35,6 +35,8 @@ entity RegFile is
|
||||
odRegA : out DATA;
|
||||
odRegB : out DATA;
|
||||
|
||||
icPC : in std_logic; -- select PC as input to RegisterFile
|
||||
idPC : in DATA;
|
||||
|
||||
icRegINsel : in std_logic_vector(4 downto 0);
|
||||
|
||||
@ -76,7 +78,11 @@ begin
|
||||
|
||||
elsif (rising_edge(iClk)) then
|
||||
if (icLoadEn = '1') then
|
||||
registerFile(to_integer(unsigned(icRegINsel))) <= idDataIn;
|
||||
if (icPC = '0') then
|
||||
registerFile(to_integer(unsigned(icRegINsel))) <= idDataIn;
|
||||
else
|
||||
registerFile(to_integer(unsigned(icRegINsel))) <= idPC;
|
||||
end if;
|
||||
sdCarry <= idCarryIn;
|
||||
sdZero <= idZeroIn;
|
||||
|
||||
|
18
src/SOC.ucf
18
src/SOC.ucf
@ -1,18 +0,0 @@
|
||||
NET clk LOC = C9; # Taktsignal Taktgenerator
|
||||
NET clk_man LOC = H18; # Manuelles Taktsignal <20>ber Taster button north
|
||||
|
||||
NET reset LOC = N17; # Reset, Schiebeschalter links
|
||||
|
||||
NET switch(0) LOC = L13; # SW0
|
||||
NET switch(1) LOC = L14; # SW1
|
||||
|
||||
NET led(0) LOC = F12;
|
||||
NET led(1) LOC = E12;
|
||||
NET led(2) LOC = E11;
|
||||
NET led(3) LOC = F11;
|
||||
NET led(4) LOC = C11;
|
||||
NET led(5) LOC = D11;
|
||||
NET led(6) LOC = E9;
|
||||
NET led(7) LOC = F9;
|
||||
|
||||
NET "clk_man" CLOCK_DEDICATED_ROUTE = FALSE;
|
261
src/SOC.vhd
261
src/SOC.vhd
@ -1,68 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library work;
|
||||
use work.cpupkg.all;
|
||||
|
||||
entity SOC is -- Testumgebung f<>r Rechner
|
||||
port(clk : in std_logic; -- Taktsignal
|
||||
clk_man : in std_logic; -- manuelles Taktsignal
|
||||
reset : in std_logic; -- Resetsignal
|
||||
led : out std_logic_vector(7 downto 0);
|
||||
switch : in std_logic_vector(1 downto 0));
|
||||
|
||||
end SOC;
|
||||
|
||||
architecture Struktur of SOC is
|
||||
|
||||
component Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
|
||||
port( clk : in std_logic; -- Taktsignal
|
||||
reset : in std_logic; -- Resetsignal
|
||||
use work.cpupkg.all;
|
||||
|
||||
entity SOC is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
|
||||
port( clk : in std_logic; -- Taktsignal
|
||||
reset : in std_logic; -- Resetsignal
|
||||
odRS232 : out std_logic;
|
||||
idRS232 : in std_logic;
|
||||
data_print_1: out DATA;
|
||||
data_print_2: out DATA); -- Ausgabe
|
||||
end component Rechner;
|
||||
|
||||
component antibeat_device is
|
||||
port (
|
||||
button_in : in std_logic; --! the button input, for example the button from an fpga
|
||||
button_out : out std_logic; --! the button output, for example going to the reset or clk of a processor
|
||||
counter : in std_logic_vector(31 downto 0); --! the number of clk ticks to wait
|
||||
clk : in std_logic; --! input clock
|
||||
reset : in std_logic
|
||||
);
|
||||
end component antibeat_device;
|
||||
|
||||
|
||||
signal data_print_1 : std_logic_vector(31 downto 0);
|
||||
signal data_print_2 : std_logic_vector(31 downto 0);
|
||||
signal sig_entprellt : std_logic;
|
||||
|
||||
signal output : std_logic_vector(15 downto 0);
|
||||
signal clk_out : std_logic;
|
||||
begin
|
||||
|
||||
-- select what to display on led
|
||||
led <= --(others => '1') when reset='1' else
|
||||
output(15 downto 8) when switch(0)='1' else
|
||||
output(7 downto 0);
|
||||
|
||||
output <= data_print_1(15 downto 0) when switch(1) = '0' else
|
||||
data_print_2(15 downto 0);
|
||||
|
||||
antibeat: antibeat_device
|
||||
port map(
|
||||
button_in => clk_man,
|
||||
button_out => clk_out,
|
||||
counter => x"019BFCC0",
|
||||
clk => clk,
|
||||
reset => reset
|
||||
);
|
||||
|
||||
|
||||
Rechner_0 : Rechner port map(clk => clk_out,
|
||||
reset => reset,
|
||||
data_print_1=> data_print_1,
|
||||
data_print_2=> data_print_2);
|
||||
|
||||
end Struktur;
|
||||
data_print_2: out DATA;
|
||||
ic200MhzClk : in std_logic
|
||||
);
|
||||
end SOC;
|
||||
|
||||
architecture arch of SOC is
|
||||
|
||||
component CPU is
|
||||
Port(
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA; --! connection to databus
|
||||
odAddress : out std_logic_vector(15 downto 0); --! connection to addressbus
|
||||
ocEnable : out std_logic; --! enable or disable RAM
|
||||
ocRnotW : out std_logic --! read/write control
|
||||
);
|
||||
end component;
|
||||
|
||||
component RAM is
|
||||
port (
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA; --! connection to databus
|
||||
idAddress : in std_logic_vector(15 downto 0); --! connection to addressbus
|
||||
icEnable : in std_logic; --! enable or disable RAM
|
||||
icRnotW : in std_logic --! read/write control
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
component MemoryMapper
|
||||
port (
|
||||
start : in std_logic_vector ( 15 downto 0 );
|
||||
stop : in std_logic_vector ( 15 downto 0 );
|
||||
adr_in : in std_logic_vector ( 15 downto 0 );
|
||||
req_in : in std_logic;
|
||||
req_out : out std_logic;
|
||||
enable : out std_logic;
|
||||
adr_out : out std_logic_vector ( 15 downto 0 )
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
component MMIO_Uart
|
||||
generic (
|
||||
GEN_start : std_logic_vector ( 15 downto 0 );
|
||||
GEN_SysClockinHz : integer;
|
||||
GEN_Baudrate : integer;
|
||||
GEN_HasExternBaudLimit : boolean
|
||||
);
|
||||
port (
|
||||
odRS232 : out std_logic;
|
||||
idRS232 : in std_logic;
|
||||
ocInterrupt : out std_logic; --! high if data is available
|
||||
odDebug : out std_logic_vector(7 downto 0);
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
bdData : inout DATA;
|
||||
idAddress : in ADDRESS;
|
||||
icEnable : in std_logic;
|
||||
icRnotW : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component clkDivider
|
||||
generic (
|
||||
GEN_FreqIn_Hz : integer;
|
||||
GEN_FreqOut_Hz : integer
|
||||
);
|
||||
port (
|
||||
iClk_in : in STD_LOGIC;
|
||||
iReset : in STD_LOGIC;
|
||||
oClk_out : out STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
signal DATAbus : std_logic_vector(31 downto 0); -- DATAbus
|
||||
signal address : std_logic_vector(15 downto 0); -- Adressbus
|
||||
signal rw_ram : std_logic; -- read/write-Signal RAM
|
||||
signal enable : std_logic;
|
||||
|
||||
signal scRAMenable : std_logic;
|
||||
signal scRAM_RnotW : std_logic;
|
||||
signal scRAM_address : std_logic_vector(15 downto 0);
|
||||
|
||||
signal scUARTenable : std_logic;
|
||||
signal scUART_RnotW : std_logic;
|
||||
signal scUART_address : std_logic_vector(15 downto 0);
|
||||
|
||||
signal scClk20Mhz : std_logic;
|
||||
|
||||
signal sdDebug : std_logic_vector(7 downto 0);
|
||||
|
||||
signal scReset : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
scReset <= not reset;
|
||||
|
||||
divider0:clkDivider
|
||||
generic map(
|
||||
GEN_FreqIn_Hz => 200000000,
|
||||
GEN_FreqOut_Hz => 20000000
|
||||
)
|
||||
port map(
|
||||
iClk_in => ic200MhzClk,
|
||||
iReset => '0',
|
||||
oClk_out => scClk20Mhz
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
CPU_1: CPU port map(
|
||||
iClk => scClk20Mhz,
|
||||
iReset => scReset,
|
||||
bdData => DATAbus,
|
||||
odAddress => address,
|
||||
ocEnable => enable,
|
||||
ocRnotW => rw_ram);
|
||||
|
||||
|
||||
|
||||
mapperRAM: MemoryMapper
|
||||
port map(
|
||||
start => x"0000",
|
||||
stop => x"00FF",
|
||||
adr_in => address,
|
||||
req_in => rw_ram,
|
||||
req_out => scRAM_RnotW,
|
||||
enable => scRAMenable,
|
||||
adr_out => scRAM_address
|
||||
);
|
||||
|
||||
|
||||
|
||||
RAM_1: RAM port map(
|
||||
iClk => scClk20Mhz,
|
||||
iReset => scReset,
|
||||
bdData => DATAbus,
|
||||
idAddress => scRAM_address,
|
||||
icEnable => scRAMenable,
|
||||
icRnotW => scRAM_RnotW);
|
||||
|
||||
|
||||
|
||||
mapperUart: MemoryMapper
|
||||
port map(
|
||||
start => x"FFF0",
|
||||
stop => x"FFF2",
|
||||
adr_in => address,
|
||||
req_in => rw_ram,
|
||||
req_out => scUART_RnotW,
|
||||
enable => scUARTenable,
|
||||
adr_out => scUART_address
|
||||
);
|
||||
|
||||
|
||||
uart0: MMIO_Uart
|
||||
generic map(
|
||||
GEN_start => x"0000",
|
||||
GEN_SysClockinHz => 20000000,
|
||||
GEN_Baudrate => 57600,
|
||||
GEN_HasExternBaudLimit => false
|
||||
)
|
||||
port map(
|
||||
odRS232 => odRS232,
|
||||
idRS232 => idRS232,
|
||||
ocInterrupt => open,
|
||||
odDebug => sdDebug,
|
||||
iClk => scClk20Mhz,
|
||||
iReset => scReset,
|
||||
bdData => DATAbus,
|
||||
idAddress => scUART_address,
|
||||
icEnable => scUARTenable,
|
||||
icRnotW => scUART_RnotW
|
||||
);
|
||||
|
||||
|
||||
data_print_1 <= DATAbus;
|
||||
data_print_2 <= x"000000" & sdDebug;
|
||||
|
||||
end arch;
|
||||
|
@ -27,14 +27,17 @@ entity Steuerwerk is
|
||||
ocLoadInstr : out std_logic; --! load instruction control signal
|
||||
ocNextPC : out std_logic; --! increment pc
|
||||
ocAddrSel : out std_logic; --! pc on addressbus
|
||||
ocJump : out std_logic --! do a ocJump
|
||||
ocJump : out std_logic; --! do a ocJump
|
||||
ocPCregister : out std_logic; --! put PC to register File
|
||||
ocUsePC : out std_logic; --! use Register to fill in the PC
|
||||
ocLoad : out std_logic --! put databus to ALU immediate port
|
||||
);
|
||||
end Steuerwerk;
|
||||
|
||||
architecture arch of Steuerwerk is
|
||||
|
||||
type STATES is (load, decode, exshl, exshr, exsto, exloa, exli, exadd, exsub, exaddc, exsubc,
|
||||
exopor, exopand, exopxor, exopnot, exjpz, exjpc, exjmp, exhlt);
|
||||
exopor, exopand, exopxor, exopnot, exjpz, exjpc, exjmp, exhlt, exjmc, exret);
|
||||
|
||||
signal sState, sState_next : STATES;
|
||||
|
||||
@ -84,7 +87,8 @@ begin
|
||||
sState_next <= load;
|
||||
end if;
|
||||
when jmp => sState_next <= exjmp;
|
||||
|
||||
when jmc => sState_next <= exjmc;
|
||||
when ret => sState_next <= exret;
|
||||
when hlt => sState_next <= exhlt;
|
||||
end case;
|
||||
when exhlt => sState_next <= exhlt;
|
||||
@ -109,6 +113,9 @@ begin
|
||||
ocNextPC <= '0'; -- do not increment pc
|
||||
ocAddrSel <= '1'; -- pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
ocPCregister <= '0'; -- do not put PC to register File
|
||||
ocUsePC <= '0';
|
||||
ocLoad <= '0';
|
||||
|
||||
when decode =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
@ -118,6 +125,9 @@ begin
|
||||
ocNextPC <= '1'; -- do not increment pc
|
||||
ocAddrSel <= '0'; -- pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
ocPCregister <= '0'; -- do not put PC to register File
|
||||
ocUsePC <= '0';
|
||||
ocLoad <= '0';
|
||||
|
||||
when exshl =>
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
@ -127,6 +137,9 @@ begin
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
ocPCregister <= '0'; -- do not put PC to register File
|
||||
ocUsePC <= '0';
|
||||
ocLoad <= '0';
|
||||
|
||||
when exshr =>
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
@ -136,7 +149,10 @@ begin
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
ocPCregister <= '0'; -- do not put PC to register File
|
||||
ocUsePC <= '0';
|
||||
ocLoad <= '0';
|
||||
|
||||