69 lines
1.8 KiB
VHDL
69 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.cpupkg.all;
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entity Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
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port( clk : in std_logic; -- Taktsignal
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reset : in std_logic; -- Resetsignal
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data_print_1: out DATA;
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data_print_2: out DATA
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);
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end Rechner;
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architecture Struktur of Rechner is
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signal DATAbus : std_logic_vector(31 downto 0); -- DATAbus
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signal address : std_logic_vector(15 downto 0); -- Adressbus
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signal rw_ram : std_logic; -- read/write-Signal RAM
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signal enable : std_logic;
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component CPU is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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bdData : inout DATA; --! connection to databus
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odAddress : out std_logic_vector(15 downto 0); --! connection to addressbus
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ocEnable : out std_logic; --! enable or disable RAM
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ocRnotW : out std_logic --! read/write control
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);
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end component;
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component RAM is
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port (
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iClk : in std_logic;
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iReset : in std_logic;
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bdData : inout DATA; --! connection to databus
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idAddress : in std_logic_vector(15 downto 0); --! connection to addressbus
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icEnable : in std_logic; --! enable or disable RAM
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icRnotW : in std_logic --! read/write control
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);
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end component;
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begin
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CPU_1: CPU port map(
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iClk => clk,
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iReset => reset,
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bdData => DATAbus,
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odAddress => address,
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ocEnable => enable,
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ocRnotW => rw_ram);
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RAM_1: RAM port map(
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iClk => clk,
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iReset => reset,
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bdData => DATAbus,
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idAddress => address,
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icEnable => enable,
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icRnotW => rw_ram);
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data_print_1 <= DATAbus; -- Ausgabe des DATAbus auf dem LCD-Display
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data_print_2 <= "0000000000000000" & address;
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end Struktur;
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