47 lines
1002 B
VHDL
47 lines
1002 B
VHDL
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--! @file
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--! @brief memory guard to only answer for the correct memory space
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--! @author Dominik Meyer
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--! @email dmeyer@hsu-hh.de
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--! @date 2013-07-18
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-------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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--! memory guard to only answer for the correct memory space
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entity MemGuard is
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generic (
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GEN_start : std_logic_vector(15 downto 0) := x"0000";
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GEN_end : std_logic_vector(15 downto 0) := x"0004"
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);
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port (
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icAddr : in std_logic_vector(15 downto 0);
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ocEnable : out std_logic
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);
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end MemGuard;
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architecture arch of MemGuard is
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begin
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process(icAddr)
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begin
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if (icAddr >= GEN_start and icAddr <= GEN_end) then
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ocEnable <= '1';
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else
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ocEnable <= '0';
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end if;
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end process;
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end arch;
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