103 lines
2.2 KiB
VHDL
103 lines
2.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:05:19 05/10/2011
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-- Design Name:
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-- Module Name: RegFile - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library work;
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use work.cpupkg.all;
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use ieee.numeric_std.all;
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entity RegFile is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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icRegAsel : in std_logic_vector(4 downto 0);
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icRegBsel : in std_logic_vector(4 downto 0);
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odRegA : out DATA;
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odRegB : out DATA;
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icPC : in std_logic; -- select PC as input to RegisterFile
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idPC : in DATA;
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icRegINsel : in std_logic_vector(4 downto 0);
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idDataIn : in DATA;
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idCarryIn : in std_logic;
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idZeroIn : in std_logic;
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icLoadEn : in std_logic;
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odCarryOut : out std_logic;
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odZeroOut : out std_logic
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);
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end RegFile;
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architecture Behavioral of RegFile is
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type registerFileType is array (0 to 31) of DATA;
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signal registerFile : registerFileType;
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signal sdData : DATA;
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signal sdCarry : std_logic;
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signal sdZero : std_logic;
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begin
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-- Execute Transition
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process(iClk, iReset)
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begin
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if (iReset = '1') then
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for i in 31 downto 0 loop
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registerFile(i) <= (others=>'0');
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end loop;
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sdCarry <= '0';
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sdZero <= '0';
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elsif (rising_edge(iClk)) then
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if (icLoadEn = '1') then
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if (icPC = '0') then
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registerFile(to_integer(unsigned(icRegINsel))) <= idDataIn;
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else
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registerFile(to_integer(unsigned(icRegINsel))) <= idPC;
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end if;
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sdCarry <= idCarryIn;
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sdZero <= idZeroIn;
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end if;
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end if;
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end process;
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odRegA <= registerFile(to_integer(unsigned(icRegAsel)));
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odRegB <= registerFile(to_integer(unsigned(icRegBsel)));
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odCarryOut <= sdCarry;
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odZeroOut <= sdZero;
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end Behavioral;
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