89 lines
2.6 KiB
VHDL
89 lines
2.6 KiB
VHDL
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-- Entity: Test
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-- Date:2013-07-18
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-- Author: byterazor
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--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity Test is
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port (
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idRS232 : in std_logic;
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odRS232 : out std_logic;
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icReset : in std_logic;
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icClk : in std_logic -- input clock, xx MHz.
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);
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end Test;
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architecture arch of Test is
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component UART
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generic (
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GEN_SysClockinHz : integer;
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GEN_Baudrate : integer;
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GEN_HasExternBaudLimit : boolean
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);
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port (
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iSysClk : in std_logic;
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ieClkEn : in std_logic;
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iReset : in std_logic;
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icBaudLExt : in integer;
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icSend : in std_logic;
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idDataSend : in std_logic_vector ( 7 downto 0 );
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ocSEmpty : out std_logic;
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ocSFull : out std_logic;
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ocSAlmostE : out std_logic;
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ocSAlmostF : out std_logic;
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odTransmit : out std_logic;
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odDataRcvd : out std_logic_vector ( 7 downto 0 );
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ocREmpty : out std_logic;
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ocRFull : out std_logic;
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ocRAlmostE : out std_logic;
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ocRAlmostF : out std_logic;
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icRReadEn : in std_logic;
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idReceive : in std_logic
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);
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end component;
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begin
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uart0: UART
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generic map(
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GEN_SysClockinHz => 100000000,
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GEN_Baudrate => GEN_Baudrate,
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GEN_HasExternBaudLimit => GEN_HasExternBaudLimit
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)
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port map(
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iSysClk => iSysClk,
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ieClkEn => ieClkEn,
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iReset => iReset,
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icBaudLExt => icBaudLExt,
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icSend => icSend,
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idDataSend => idDataSend,
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ocSEmpty => ocSEmpty,
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ocSFull => ocSFull,
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ocSAlmostE => ocSAlmostE,
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ocSAlmostF => ocSAlmostF,
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odTransmit => odTransmit,
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odDataRcvd => odDataRcvd,
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ocREmpty => ocREmpty,
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ocRFull => ocRFull,
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ocRAlmostE => ocRAlmostE,
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ocRAlmostF => ocRAlmostF,
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icRReadEn => icRReadEn,
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idReceive => idReceive
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);
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end arch;
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