Commit Graph

21 Commits

Author SHA1 Message Date
5cbcbdd04f FIX: fixed wrong instantiation of SimpleFiFo 2014-02-08 21:42:33 +01:00
8748f946ab ADD: rebuild to support different top modules for different FPGA boards 2014-02-08 21:41:57 +01:00
bf2cba5f78 ADD: added UCF file for spartan 3e starter kit 2014-02-08 17:13:38 +01:00
6b9c4576b8 ADD: added assembler program for printing Geraffel Processor 2014-01-07 21:35:13 +01:00
c0031f415c CHG: changed initial Program to print Geraffel Processor 2014-01-07 21:34:30 +01:00
0be13ee269 FIX: fixed Makefile for ML505 Board 2014-01-07 21:33:36 +01:00
86df98dc86 ADD: UCF file for Xilinx ML505 Evaluation Board 2014-01-07 21:33:07 +01:00
4f00cedb90 ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
dbd8ef11a1 ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs 2014-01-05 02:52:21 +01:00
b02a2f5b75 RM: removed not needed file 2014-01-05 02:34:48 +01:00
8b9f707b41 ADD: UCF File for ML505 Evaluation Board 2013-12-30 15:22:13 +01:00
69e1ffe919 FIX: license and author information, signal name changes 2013-12-30 15:11:56 +01:00
75dbc9f109 FIX: fixed signal name changes 2013-12-30 15:11:22 +01:00
aa3ed4c103 FIX: fixed file headers, added licence, formated code 2013-12-30 14:56:42 +01:00
2ff599262a RM: removed unused components 2013-12-30 14:47:52 +01:00
63c900fc12 FIX: found bug in Processor core 2013-07-29 09:25:06 +02:00
c46379c117 some improvements 2013-07-26 12:33:01 +02:00
a53abe0ff9 FIX: fixes and ADD: small assembler 2013-07-04 16:17:05 +02:00
bc07966401 IMPROVE: extended to 32bit data and 16bit address, fixed li instruction 2013-07-02 23:25:46 +02:00
533bae3e02 ADD: added load immidiate instruction, added UART sources 2013-07-02 22:32:18 +02:00
6cb6930f68 ADD: files from university processor core 2013-07-02 22:15:26 +02:00