65 lines
2.2 KiB
VHDL
65 lines
2.2 KiB
VHDL
--------------------------------------------------------------------------------
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-- Entity: ClkEnable
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--------------------------------------------------------------------------------
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-- Copyright ... 2011
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-- Filename : ClkEnable.vhd
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-- Creation date : 2012-04-06
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-- Author(s) : marcel eckert (eckert@hsu-hh.de)
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--------------------------------------------------------------------------------
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--! @file
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--! @brief Implements a generic ClkEnable generator
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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--! brief Implements a generic ClkEnable generator
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--! detailed Implements a generic ClkEnable generator. Based on an input frequency
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--! <GEN_FreqIn_Hz>, an output enable (1 <GEN_FreqIn_Hz> period) is generated every
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--! <GEN_FreqOut_Hz> periods
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entity clkEnable is
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generic(
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GEN_FreqIn_Hz : integer := 200000000; --! signal description input clock frequency in Hz for <iClkIn>
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GEN_FreqOut_Hz : integer := 100000000 --! signal description output clock frequency in Hz for <oClkEn>
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);
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port (
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iClkin : in STD_LOGIC; --! signal description input clock
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iReset : in STD_LOGIC; --! signal description synchronous reset (should be tied to '0')
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oeClkEn : out STD_LOGIC --! signal description output clockEnable
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);
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end clkEnable;
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architecture Behavioral of clkEnable is
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constant cLimit : integer := GEN_FreqIn_Hz / GEN_FreqOut_Hz;
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signal sCounter : integer range 0 to (cLimit-1) := 0;
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signal seClkEn : STD_LOGIC := '1';
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begin
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process (iClkIn)
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begin
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if (rising_edge(iClkIn)) then
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if (iReset = '1') then
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sCounter <= 0;
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seClkEn <= '1';
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elsif (sCounter = (cLimit-1)) then
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sCounter <= 0;
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seClkEn <= '1';
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else
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sCounter <= sCounter + 1;
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seClkEn <= '0';
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end if;
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end if;
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end process;
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oeClkEn <= seClkEn;
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end Behavioral;
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