96 lines
3.3 KiB
VHDL
96 lines
3.3 KiB
VHDL
-------------------------------------------------------
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--! @file
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--! @brief RegisterFile for the Simple Processor Core (Geraffel Processor)
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--! @author Dominik Meyer
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--! @email dmeyer@federationhq.de
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--! @licence GPLv2
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--! @date unknown
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-------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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library work;
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use work.cpupkg.all;
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use ieee.numeric_std.all;
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--! RegisterFile for the Simple Processor Core (Geraffel Processor)
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--!
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--! This Code is based on a processor core used at the Helmut Schmidt University for
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--! educational purposes.
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--!
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entity RegFile is
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port(
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iClk : in std_logic; --! main sytem clock signal
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iReset : in std_logic; --! main system active high reset
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icRegAsel : in std_logic_vector(4 downto 0); --! address of register A
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icRegBsel : in std_logic_vector(4 downto 0); --! address of register B
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odRegA : out DATA; --! output of the register A Value
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odRegB : out DATA; --! output of the register B Value
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icPC : in std_logic; --! select the PC Input as the input value, required for ret instruction
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idPC : in DATA; --! input of the PC, required for the ret instruction
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icRegINsel : in std_logic_vector(4 downto 0); --! address of the register to which to save the input
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idDataIn : in DATA; --! data input, normally from the ALU
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idCarryIn : in std_logic; --! Carry Flag of the last Operation
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idZeroIn : in std_logic; --! Zero Flag of the last Operation
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icLoadEn : in std_logic; --! actually save the input Data to the selected register
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odCarryOut : out std_logic; --! output of the currently saved carry flag
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odZeroOut : out std_logic --! output of the currently saved zero flag
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);
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end RegFile;
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architecture Behavioral of RegFile is
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type registerFileType is array (0 to 31) of DATA;
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signal registerFile : registerFileType;
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signal sdData : DATA;
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signal sdCarry : std_logic;
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signal sdZero : std_logic;
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begin
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-- Execute Transition
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process(iClk, iReset)
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begin
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if (iReset = '1') then
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for i in 31 downto 0 loop
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registerFile(i) <= (others => '0');
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end loop;
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sdCarry <= '0';
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sdZero <= '0';
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elsif (rising_edge(iClk)) then
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if (icLoadEn = '1') then
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if (icPC = '0') then
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registerFile(to_integer(unsigned(icRegINsel))) <= idDataIn;
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else
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registerFile(to_integer(unsigned(icRegINsel))) <= idPC;
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end if;
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sdCarry <= idCarryIn;
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sdZero <= idZeroIn;
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end if;
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end if;
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end process;
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odRegA <= registerFile(to_integer(unsigned(icRegAsel)));
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odRegB <= registerFile(to_integer(unsigned(icRegBsel)));
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odCarryOut <= sdCarry;
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odZeroOut <= sdZero;
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end Behavioral;
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