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9c3c888ca8
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FIX: fixed Testbench to support new SOC port interface
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2014-02-08 21:45:46 +01:00 |
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4703b50e8f
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FIX: corrected description of RAM so, that block ram is used to implement it
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2014-02-08 21:45:11 +01:00 |
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5cbcbdd04f
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FIX: fixed wrong instantiation of SimpleFiFo
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2014-02-08 21:42:33 +01:00 |
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8748f946ab
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ADD: rebuild to support different top modules for different FPGA boards
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2014-02-08 21:41:57 +01:00 |
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c0031f415c
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CHG: changed initial Program to print Geraffel Processor
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2014-01-07 21:34:30 +01:00 |
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4f00cedb90
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ADD: switched to a fork of the used UART
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2014-01-05 03:14:50 +01:00 |
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dbd8ef11a1
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ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs
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2014-01-05 02:52:21 +01:00 |
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b02a2f5b75
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RM: removed not needed file
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2014-01-05 02:34:48 +01:00 |
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69e1ffe919
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FIX: license and author information, signal name changes
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2013-12-30 15:11:56 +01:00 |
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75dbc9f109
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FIX: fixed signal name changes
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2013-12-30 15:11:22 +01:00 |
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aa3ed4c103
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FIX: fixed file headers, added licence, formated code
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2013-12-30 14:56:42 +01:00 |
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2ff599262a
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RM: removed unused components
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2013-12-30 14:47:52 +01:00 |
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63c900fc12
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FIX: found bug in Processor core
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2013-07-29 09:25:06 +02:00 |
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c46379c117
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some improvements
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2013-07-26 12:33:01 +02:00 |
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a53abe0ff9
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FIX: fixes and ADD: small assembler
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2013-07-04 16:17:05 +02:00 |
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bc07966401
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IMPROVE: extended to 32bit data and 16bit address, fixed li instruction
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2013-07-02 23:25:46 +02:00 |
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533bae3e02
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ADD: added load immidiate instruction, added UART sources
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2013-07-02 22:32:18 +02:00 |
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6cb6930f68
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ADD: files from university processor core
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2013-07-02 22:15:26 +02:00 |
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