Commit Graph

21 Commits

Author SHA1 Message Date
Dominik Meyer f2da12bbfe FIX: fixed some bugs 2014-12-03 21:57:49 +01:00
Dominik Meyer 94b1a4541a FIX: fixed working of TestBench 2014-02-09 13:56:47 +01:00
Dominik Meyer 7d23cf7e98 ADD: top module+ucf file for using processor on an ML 505 FPGA Board 2014-02-08 22:48:17 +01:00
Dominik Meyer 9c3c888ca8 FIX: fixed Testbench to support new SOC port interface 2014-02-08 21:45:46 +01:00
Dominik Meyer 4703b50e8f FIX: corrected description of RAM so, that block ram is used to implement it 2014-02-08 21:45:11 +01:00
Dominik Meyer 5cbcbdd04f FIX: fixed wrong instantiation of SimpleFiFo 2014-02-08 21:42:33 +01:00
Dominik Meyer 8748f946ab ADD: rebuild to support different top modules for different FPGA boards 2014-02-08 21:41:57 +01:00
Dominik Meyer c0031f415c CHG: changed initial Program to print Geraffel Processor 2014-01-07 21:34:30 +01:00
Dominik Meyer 4f00cedb90 ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
Dominik Meyer dbd8ef11a1 ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs 2014-01-05 02:52:21 +01:00
Dominik Meyer b02a2f5b75 RM: removed not needed file 2014-01-05 02:34:48 +01:00
Dominik Meyer 69e1ffe919 FIX: license and author information, signal name changes 2013-12-30 15:11:56 +01:00
Dominik Meyer 75dbc9f109 FIX: fixed signal name changes 2013-12-30 15:11:22 +01:00
Dominik Meyer aa3ed4c103 FIX: fixed file headers, added licence, formated code 2013-12-30 14:56:42 +01:00
Dominik Meyer 2ff599262a RM: removed unused components 2013-12-30 14:47:52 +01:00
Dominik Meyer 63c900fc12 FIX: found bug in Processor core 2013-07-29 09:25:06 +02:00
Dominik Meyer c46379c117 some improvements 2013-07-26 12:33:01 +02:00
Dominik Meyer a53abe0ff9 FIX: fixes and ADD: small assembler 2013-07-04 16:17:05 +02:00
Dominik Meyer bc07966401 IMPROVE: extended to 32bit data and 16bit address, fixed li instruction 2013-07-02 23:25:46 +02:00
Dominik Meyer 533bae3e02 ADD: added load immidiate instruction, added UART sources 2013-07-02 22:32:18 +02:00
Dominik Meyer 6cb6930f68 ADD: files from university processor core 2013-07-02 22:15:26 +02:00