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IMPROVE: extended to 32bit data and 16bit address, fixed li instruction

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This commit is contained in:
Dominik Meyer 2013-07-02 23:25:46 +02:00
parent 533bae3e02
commit bc07966401
9 changed files with 72 additions and 58 deletions
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4
Makefile.files
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@ -1,4 +1,4 @@
VHDL_PKG += src/cpupkg.vhd
VHDL_TB += src/Rechner.vhd
VHDL_TB += src/TBRechner.vhd
VHDL_SRC += src/RegFile.vhd src/CPU.vhd src/MemInterface.vhd src/antibeat_device.vhd src/FetchDecode.vhd src/ALU.vhd src/RAM.vhd
VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd
VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd src/Rechner.vhd

12
src/ALU.vhd
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@ -48,7 +48,7 @@ entity ALU is
end ALU;
architecture Behavioral of ALU is
signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(16 downto 0);
signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(32 downto 0);
begin
sdOp1 <= '0' & idOperand1;
sdOp2 <= '0' & idOperand2;
@ -56,10 +56,10 @@ begin
process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate)
begin
if (icOperation = shl) then
sdTempResult <= sdOp1(15 downto 0) & "0";
sdTempResult <= sdOp1(31 downto 0) & "0";
elsif (icOperation = shr) then
sdTempResult <= sdOp1(0) & "0" & sdOp1(15 downto 1);
sdTempResult <= sdOp1(0) & "0" & sdOp1(31 downto 1);
elsif (icOperation = sto) then
sdTempResult <= (others => '-');
@ -107,9 +107,9 @@ begin
end if;
end process;
odResult <= sdTempResult(15 downto 0);
odCarryOut <= sdTempResult(16);
odZeroOut <= '1' when sdTempResult(15 downto 0) = "0000000000000000" else
odResult <= sdTempResult(31 downto 0);
odCarryOut <= sdTempResult(32);
odZeroOut <= '1' when sdTempResult(31 downto 0) = 0 else
'0';
end Behavioral;

40
src/FetchDecode.vhd
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@ -66,27 +66,28 @@ begin
scOp_next <= scOp;
sdImmidiate_next <= sdImmidate;
--! ISA Definition
if (icLoadInstr = '1') then
sdAdr_next <= idData(11 downto 0);
sdImmidiate_next <= "0000" & idData(11 downto 0);
sdAdr_next <= idData(15 downto 0);
sdImmidiate_next <= "0000000000000000" & idData(15 downto 0);
case idData(15 downto 12) is
when "0000" => scOp_next <= shl;
when "0001" => scOp_next <= shr;
when "0010" => scOp_next <= sto;
when "0011" => scOp_next <= loa;
when "0100" => scOp_next <= add;
when "0101" => scOp_next <= sub;
when "0110" => scOp_next <= addc;
when "0111" => scOp_next <= subc;
when "1000" => scOp_next <= opor;
when "1001" => scOp_next <= opand;
when "1010" => scOp_next <= opxor;
when "1011" => scOp_next <= opnot;
when "1100" => scOp_next <= jpz;
when "1101" => scOp_next <= jpc;
when "1110" => scOp_next <= jmp;
when "1111" => scOP_next <= li;
case idData(31 downto 26) is
when "000000" => scOp_next <= shl;
when "000001" => scOp_next <= shr;
when "000010" => scOp_next <= sto;
when "000011" => scOp_next <= loa;
when "000100" => scOp_next <= add;
when "000101" => scOp_next <= sub;
when "000110" => scOp_next <= addc;
when "000111" => scOp_next <= subc;
when "001000" => scOp_next <= opor;
when "001001" => scOp_next <= opand;
when "001010" => scOp_next <= opxor;
when "001011" => scOp_next <= opnot;
when "001100" => scOp_next <= jpz;
when "001101" => scOp_next <= jpc;
when "001110" => scOp_next <= jmp;
when "001111" => scOP_next <= li;
when others => scOp_next <= hlt;
end case;
end if;
@ -129,5 +130,6 @@ begin
ocOperation <= scOp when icLoadInstr = '0' else
scOp_next;
odImmidiate <= sdImmidate when icLoadInstr = '0' else sdImmidiate_next;
end Behavioral;

31
src/RAM.vhd
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@ -33,20 +33,23 @@ architecture arch of RAM is
type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
constant Prog1 : MEMORY := ( --! 4k * 16bit of RAM
0 => B"0011_000000001010", -- loa 10 (n)
1 => B"1100_000000001000", -- jpz 8
2 => B"0101_000000001100", -- sub <1>
3 => B"0010_000000001010", -- sto 10 (n)
4 => B"0011_000000001011", -- loa 11 (a)
5 => B"0100_000000001001", -- add <result>
6 => B"0010_000000001001", -- sto <result>
7 => B"1110_000000000000", -- jmp 0
8 => B"1111_000000000000", -- hlt
9 => B"0000_000000000000", -- result
10 => B"0000_000000000011", -- n=3
11 => B"0000_000000000101", -- a=1
12 => B"0000_000000000001", -- 1
constant Prog1 : MEMORY := ( --! 4k * 32bit of RAM
0 => B"001111_000_000_000_0_0000000000000101", -- li 5
1 => B"000010_000_000_000_0_0000000000100000", -- sto 32
2 => B"111111_000_000_000_0_0000000000000000", -- hlt
-- 0 => B"0011_000000001010", -- loa 10 (n)
-- 1 => B"1100_000000001000", -- jpz 8
-- 2 => B"0101_000000001100", -- sub <1>
-- 3 => B"0010_000000001010", -- sto 10 (n)
-- 4 => B"0011_000000001011", -- loa 11 (a)
-- 5 => B"0100_000000001001", -- add <result>
-- 6 => B"0010_000000001001", -- sto <result>
-- 7 => B"1110_000000000000", -- jmp 0
-- 8 => B"1111_000000000000", -- hlt
-- 9 => B"0000_000000000000", -- result
-- 10 => B"0000_000000000011", -- n=3
-- 11 => B"0000_000000000101", -- a=1
-- 12 => B"0000_000000000001", -- 1
others => (others => '0')

10
src/Rechner.vhd
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@ -14,8 +14,8 @@ end Rechner;
architecture Struktur of Rechner is
signal DATAbus : std_logic_vector(15 downto 0); -- DATAbus
signal address : std_logic_vector(11 downto 0); -- Adressbus
signal DATAbus : std_logic_vector(31 downto 0); -- DATAbus
signal address : std_logic_vector(15 downto 0); -- Adressbus
signal rw_ram : std_logic; -- read/write-Signal RAM
signal enable : std_logic;
@ -24,7 +24,7 @@ architecture Struktur of Rechner is
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
odAddress : out std_logic_vector(11 downto 0); --! connection to addressbus
odAddress : out std_logic_vector(15 downto 0); --! connection to addressbus
ocEnable : out std_logic; --! enable or disable RAM
ocRnotW : out std_logic --! read/write control
);
@ -35,7 +35,7 @@ architecture Struktur of Rechner is
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
idAddress : in std_logic_vector(11 downto 0); --! connection to addressbus
idAddress : in std_logic_vector(15 downto 0); --! connection to addressbus
icEnable : in std_logic; --! enable or disable RAM
icRnotW : in std_logic --! read/write control
@ -63,6 +63,6 @@ begin
icRnotW => rw_ram);
data_print_1 <= DATAbus; -- Ausgabe des DATAbus auf dem LCD-Display
data_print_2 <= "0000" & address;
data_print_2 <= "0000000000000000" & address;
end Struktur;

8
src/SOC.vhd
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@ -34,8 +34,8 @@ component antibeat_device is
end component antibeat_device;
signal data_print_1 : std_logic_vector(15 downto 0);
signal data_print_2 : std_logic_vector(15 downto 0);
signal data_print_1 : std_logic_vector(31 downto 0);
signal data_print_2 : std_logic_vector(31 downto 0);
signal sig_entprellt : std_logic;
signal output : std_logic_vector(15 downto 0);
@ -47,8 +47,8 @@ begin
output(15 downto 8) when switch(0)='1' else
output(7 downto 0);
output <= data_print_1 when switch(1) = '0' else
data_print_2;
output <= data_print_1(15 downto 0) when switch(1) = '0' else
data_print_2(15 downto 0);
antibeat: antibeat_device
port map(

9
src/Steuerwerk.vhd
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@ -155,6 +155,15 @@ begin
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exli =>
ocRnotWRam <= '0'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exadd =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result

8
src/TBRechner.vhd
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@ -43,8 +43,8 @@ ARCHITECTURE behavior OF TBRechner IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
data_print_1 : OUT std_logic_vector(15 downto 0);
data_print_2 : OUT std_logic_vector(15 downto 0)
data_print_1 : OUT std_logic_vector(31 downto 0);
data_print_2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
@ -52,8 +52,8 @@ ARCHITECTURE behavior OF TBRechner IS
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal data_print_1 : std_logic_vector(15 downto 0);
signal data_print_2 : std_logic_vector(15 downto 0);
signal data_print_1 : std_logic_vector(31 downto 0);
signal data_print_2 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;

4
src/cpupkg.vhd
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@ -10,8 +10,8 @@ use IEEE.STD_LOGIC_1164.all;
package cpupkg is
type OPTYPE is (shl, shr, sto, loa, li, add, sub, addc, subc, opor, opand, opxor, opnot, jpz, jpc, jmp, hlt);
subtype DATA is std_logic_vector(15 downto 0);
subtype ADDRESS is std_logic_vector(11 downto 0);
subtype DATA is std_logic_vector(31 downto 0);
subtype ADDRESS is std_logic_vector(15 downto 0);
end cpupkg;