From bc0796640161a189a6b42c0f1030b03d9da5cf74 Mon Sep 17 00:00:00 2001 From: Dominik Meyer Date: Tue, 2 Jul 2013 23:25:46 +0200 Subject: [PATCH] IMPROVE: extended to 32bit data and 16bit address, fixed li instruction --- Makefile.files | 4 ++-- src/ALU.vhd | 12 ++++++------ src/FetchDecode.vhd | 44 +++++++++++++++++++++++--------------------- src/RAM.vhd | 31 +++++++++++++++++-------------- src/Rechner.vhd | 10 +++++----- src/SOC.vhd | 8 ++++---- src/Steuerwerk.vhd | 9 +++++++++ src/TBRechner.vhd | 8 ++++---- src/cpupkg.vhd | 4 ++-- 9 files changed, 72 insertions(+), 58 deletions(-) diff --git a/Makefile.files b/Makefile.files index 2cdb787..21a641e 100644 --- a/Makefile.files +++ b/Makefile.files @@ -1,4 +1,4 @@ VHDL_PKG += src/cpupkg.vhd -VHDL_TB += src/Rechner.vhd +VHDL_TB += src/TBRechner.vhd VHDL_SRC += src/RegFile.vhd src/CPU.vhd src/MemInterface.vhd src/antibeat_device.vhd src/FetchDecode.vhd src/ALU.vhd src/RAM.vhd -VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd +VHDL_SRC += src/SOC.vhd src/Steuerwerk.vhd src/Rechner.vhd diff --git a/src/ALU.vhd b/src/ALU.vhd index 39e9ef2..342397c 100644 --- a/src/ALU.vhd +++ b/src/ALU.vhd @@ -48,7 +48,7 @@ entity ALU is end ALU; architecture Behavioral of ALU is - signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(16 downto 0); + signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(32 downto 0); begin sdOp1 <= '0' & idOperand1; sdOp2 <= '0' & idOperand2; @@ -56,10 +56,10 @@ begin process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate) begin if (icOperation = shl) then - sdTempResult <= sdOp1(15 downto 0) & "0"; + sdTempResult <= sdOp1(31 downto 0) & "0"; elsif (icOperation = shr) then - sdTempResult <= sdOp1(0) & "0" & sdOp1(15 downto 1); + sdTempResult <= sdOp1(0) & "0" & sdOp1(31 downto 1); elsif (icOperation = sto) then sdTempResult <= (others => '-'); @@ -107,9 +107,9 @@ begin end if; end process; - odResult <= sdTempResult(15 downto 0); - odCarryOut <= sdTempResult(16); - odZeroOut <= '1' when sdTempResult(15 downto 0) = "0000000000000000" else + odResult <= sdTempResult(31 downto 0); + odCarryOut <= sdTempResult(32); + odZeroOut <= '1' when sdTempResult(31 downto 0) = 0 else '0'; end Behavioral; diff --git a/src/FetchDecode.vhd b/src/FetchDecode.vhd index 5eab6c7..add2554 100644 --- a/src/FetchDecode.vhd +++ b/src/FetchDecode.vhd @@ -65,28 +65,29 @@ begin sdPC_next <= sdPC; scOp_next <= scOp; sdImmidiate_next <= sdImmidate; - + + --! ISA Definition if (icLoadInstr = '1') then - sdAdr_next <= idData(11 downto 0); - sdImmidiate_next <= "0000" & idData(11 downto 0); + sdAdr_next <= idData(15 downto 0); + sdImmidiate_next <= "0000000000000000" & idData(15 downto 0); - case idData(15 downto 12) is - when "0000" => scOp_next <= shl; - when "0001" => scOp_next <= shr; - when "0010" => scOp_next <= sto; - when "0011" => scOp_next <= loa; - when "0100" => scOp_next <= add; - when "0101" => scOp_next <= sub; - when "0110" => scOp_next <= addc; - when "0111" => scOp_next <= subc; - when "1000" => scOp_next <= opor; - when "1001" => scOp_next <= opand; - when "1010" => scOp_next <= opxor; - when "1011" => scOp_next <= opnot; - when "1100" => scOp_next <= jpz; - when "1101" => scOp_next <= jpc; - when "1110" => scOp_next <= jmp; - when "1111" => scOP_next <= li; + case idData(31 downto 26) is + when "000000" => scOp_next <= shl; + when "000001" => scOp_next <= shr; + when "000010" => scOp_next <= sto; + when "000011" => scOp_next <= loa; + when "000100" => scOp_next <= add; + when "000101" => scOp_next <= sub; + when "000110" => scOp_next <= addc; + when "000111" => scOp_next <= subc; + when "001000" => scOp_next <= opor; + when "001001" => scOp_next <= opand; + when "001010" => scOp_next <= opxor; + when "001011" => scOp_next <= opnot; + when "001100" => scOp_next <= jpz; + when "001101" => scOp_next <= jpc; + when "001110" => scOp_next <= jmp; + when "001111" => scOP_next <= li; when others => scOp_next <= hlt; end case; end if; @@ -128,6 +129,7 @@ begin ocOperation <= scOp when icLoadInstr = '0' else scOp_next; - + + odImmidiate <= sdImmidate when icLoadInstr = '0' else sdImmidiate_next; end Behavioral; diff --git a/src/RAM.vhd b/src/RAM.vhd index 42da817..37dd909 100644 --- a/src/RAM.vhd +++ b/src/RAM.vhd @@ -33,20 +33,23 @@ architecture arch of RAM is type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words - constant Prog1 : MEMORY := ( --! 4k * 16bit of RAM - 0 => B"0011_000000001010", -- loa 10 (n) - 1 => B"1100_000000001000", -- jpz 8 - 2 => B"0101_000000001100", -- sub <1> - 3 => B"0010_000000001010", -- sto 10 (n) - 4 => B"0011_000000001011", -- loa 11 (a) - 5 => B"0100_000000001001", -- add - 6 => B"0010_000000001001", -- sto - 7 => B"1110_000000000000", -- jmp 0 - 8 => B"1111_000000000000", -- hlt - 9 => B"0000_000000000000", -- result - 10 => B"0000_000000000011", -- n=3 - 11 => B"0000_000000000101", -- a=1 - 12 => B"0000_000000000001", -- 1 + constant Prog1 : MEMORY := ( --! 4k * 32bit of RAM + 0 => B"001111_000_000_000_0_0000000000000101", -- li 5 + 1 => B"000010_000_000_000_0_0000000000100000", -- sto 32 + 2 => B"111111_000_000_000_0_0000000000000000", -- hlt + -- 0 => B"0011_000000001010", -- loa 10 (n) + -- 1 => B"1100_000000001000", -- jpz 8 + -- 2 => B"0101_000000001100", -- sub <1> + -- 3 => B"0010_000000001010", -- sto 10 (n) + -- 4 => B"0011_000000001011", -- loa 11 (a) + -- 5 => B"0100_000000001001", -- add + -- 6 => B"0010_000000001001", -- sto + -- 7 => B"1110_000000000000", -- jmp 0 + -- 8 => B"1111_000000000000", -- hlt + -- 9 => B"0000_000000000000", -- result + -- 10 => B"0000_000000000011", -- n=3 + -- 11 => B"0000_000000000101", -- a=1 + -- 12 => B"0000_000000000001", -- 1 others => (others => '0') diff --git a/src/Rechner.vhd b/src/Rechner.vhd index 4c35c85..8c2c0cb 100644 --- a/src/Rechner.vhd +++ b/src/Rechner.vhd @@ -14,8 +14,8 @@ end Rechner; architecture Struktur of Rechner is - signal DATAbus : std_logic_vector(15 downto 0); -- DATAbus - signal address : std_logic_vector(11 downto 0); -- Adressbus + signal DATAbus : std_logic_vector(31 downto 0); -- DATAbus + signal address : std_logic_vector(15 downto 0); -- Adressbus signal rw_ram : std_logic; -- read/write-Signal RAM signal enable : std_logic; @@ -24,7 +24,7 @@ architecture Struktur of Rechner is iClk : in std_logic; iReset : in std_logic; bdData : inout DATA; --! connection to databus - odAddress : out std_logic_vector(11 downto 0); --! connection to addressbus + odAddress : out std_logic_vector(15 downto 0); --! connection to addressbus ocEnable : out std_logic; --! enable or disable RAM ocRnotW : out std_logic --! read/write control ); @@ -35,7 +35,7 @@ architecture Struktur of Rechner is iClk : in std_logic; iReset : in std_logic; bdData : inout DATA; --! connection to databus - idAddress : in std_logic_vector(11 downto 0); --! connection to addressbus + idAddress : in std_logic_vector(15 downto 0); --! connection to addressbus icEnable : in std_logic; --! enable or disable RAM icRnotW : in std_logic --! read/write control @@ -63,6 +63,6 @@ begin icRnotW => rw_ram); data_print_1 <= DATAbus; -- Ausgabe des DATAbus auf dem LCD-Display - data_print_2 <= "0000" & address; + data_print_2 <= "0000000000000000" & address; end Struktur; diff --git a/src/SOC.vhd b/src/SOC.vhd index 2e427c3..f994464 100644 --- a/src/SOC.vhd +++ b/src/SOC.vhd @@ -34,8 +34,8 @@ component antibeat_device is end component antibeat_device; -signal data_print_1 : std_logic_vector(15 downto 0); -signal data_print_2 : std_logic_vector(15 downto 0); +signal data_print_1 : std_logic_vector(31 downto 0); +signal data_print_2 : std_logic_vector(31 downto 0); signal sig_entprellt : std_logic; signal output : std_logic_vector(15 downto 0); @@ -47,8 +47,8 @@ begin output(15 downto 8) when switch(0)='1' else output(7 downto 0); - output <= data_print_1 when switch(1) = '0' else - data_print_2; + output <= data_print_1(15 downto 0) when switch(1) = '0' else + data_print_2(15 downto 0); antibeat: antibeat_device port map( diff --git a/src/Steuerwerk.vhd b/src/Steuerwerk.vhd index b10aeb9..f3b9aef 100644 --- a/src/Steuerwerk.vhd +++ b/src/Steuerwerk.vhd @@ -154,6 +154,15 @@ begin ocNextPC <= '0'; -- increment pc ocAddrSel <= '0'; -- no pc on addressbus ocJump <= '0'; -- no ocJump + + when exli => + ocRnotWRam <= '0'; -- read from RAM + ocLoadEn <= '1'; -- save result + ocEnableRAM <= '0'; -- do not put akku on databus + ocLoadInstr <= '0'; -- do not load instruction + ocNextPC <= '0'; -- increment pc + ocAddrSel <= '0'; -- no pc on addressbus + ocJump <= '0'; -- no ocJump when exadd => ocRnotWRam <= '1'; -- read from RAM diff --git a/src/TBRechner.vhd b/src/TBRechner.vhd index ce47a92..ce7158b 100644 --- a/src/TBRechner.vhd +++ b/src/TBRechner.vhd @@ -43,8 +43,8 @@ ARCHITECTURE behavior OF TBRechner IS PORT( clk : IN std_logic; reset : IN std_logic; - data_print_1 : OUT std_logic_vector(15 downto 0); - data_print_2 : OUT std_logic_vector(15 downto 0) + data_print_1 : OUT std_logic_vector(31 downto 0); + data_print_2 : OUT std_logic_vector(31 downto 0) ); END COMPONENT; @@ -52,8 +52,8 @@ ARCHITECTURE behavior OF TBRechner IS --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '1'; - signal data_print_1 : std_logic_vector(15 downto 0); - signal data_print_2 : std_logic_vector(15 downto 0); + signal data_print_1 : std_logic_vector(31 downto 0); + signal data_print_2 : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; diff --git a/src/cpupkg.vhd b/src/cpupkg.vhd index a374a8d..60f7cdb 100644 --- a/src/cpupkg.vhd +++ b/src/cpupkg.vhd @@ -10,8 +10,8 @@ use IEEE.STD_LOGIC_1164.all; package cpupkg is type OPTYPE is (shl, shr, sto, loa, li, add, sub, addc, subc, opor, opand, opxor, opnot, jpz, jpc, jmp, hlt); - subtype DATA is std_logic_vector(15 downto 0); - subtype ADDRESS is std_logic_vector(11 downto 0); + subtype DATA is std_logic_vector(31 downto 0); + subtype ADDRESS is std_logic_vector(15 downto 0); end cpupkg;