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FIX: fixed Testbench to support new SOC port interface

This commit is contained in:
Dominik Meyer 2014-02-08 21:45:46 +01:00
parent 4703b50e8f
commit 9c3c888ca8
1 changed files with 8 additions and 14 deletions
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22
src/TBRechner.vhd
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@ -41,13 +41,11 @@ ARCHITECTURE behavior OF TBRechner IS
COMPONENT SOC COMPONENT SOC
PORT( PORT(
clk : IN std_logic; icclk : IN std_logic;
reset : IN std_logic; icreset : IN std_logic;
odLED : out std_logic_vector(7 downto 0);
odRS232 : out std_logic; odRS232 : out std_logic;
idRS232 : in std_logic; idRS232 : in std_logic
ic200MhzClk : in std_logic;
data_print_1 : OUT std_logic_vector(31 downto 0);
data_print_2 : OUT std_logic_vector(31 downto 0)
); );
END COMPONENT; END COMPONENT;
@ -55,8 +53,6 @@ ARCHITECTURE behavior OF TBRechner IS
--Inputs --Inputs
signal clk : std_logic := '0'; signal clk : std_logic := '0';
signal reset : std_logic := '0'; signal reset : std_logic := '0';
signal data_print_1 : std_logic_vector(31 downto 0);
signal data_print_2 : std_logic_vector(31 downto 0);
signal idRS232, odRS232 : std_logic; signal idRS232, odRS232 : std_logic;
@ -67,13 +63,11 @@ BEGIN
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: SOC PORT MAP ( uut: SOC PORT MAP (
clk => clk, icclk => clk,
ic200MhzClk => clk, icreset => reset,
reset => reset, odLED => open,
idRS232 => idRS232, idRS232 => idRS232,
odRS232 => odRS232, odRS232 => odRS232
data_print_1 => data_print_1,
data_print_2 => data_print_2
); );
-- Clock process definitions -- Clock process definitions