FIX: license and author information, signal name changes
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src/CPU.vhd
429
src/CPU.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:51:48 05/11/2011
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-- Design Name:
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-- Module Name: CPU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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-------------------------------------------------------
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--! @file
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--! @brief CPU Core of the Simple Processor Core (Geraffel Processor)
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--! @author Dominik Meyer/ Marcel Eckert
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--! @email dmeyer@federationhq.de
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--! @licence GPLv2
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--! @date unknown
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-------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.all;
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library work;
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use work.cpupkg.all;
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use work.cpupkg.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--! CPU Core of the Simple Processor Core (Geraffel Processor)
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--!
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--! This Code is based on a processor core used at the Helmut Schmidt University for
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--! educational purposes.
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--!
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entity CPU is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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bdData : inout DATA; --! connection to databus
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odAddress : out ADDRESS; --! connection to addressbus
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ocEnable : out std_logic; --! enable or disable RAM
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ocRnotW : out std_logic --! read/write control
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);
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port(
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iClk : in std_logic; --! main system clock
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iReset : in std_logic; --! system active high reset
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bdData : inout DATA; --! connection to databus
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odAddress : out ADDRESS; --! connection to addressbus
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ocEnable : out std_logic; --! enable or disable RAM
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ocRnotW : out std_logic --! read/write control
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);
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end CPU;
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architecture Behavioral of CPU is
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component Steuerwerk is
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port (
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iClk : in std_logic; --! iClk signal
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iReset : in std_logic; --! iReset signal
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icOpCode : in optype; --! icOpCode bus
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idCarry : in std_logic; --! carry from register file
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idZero : in std_logic; --! zero flag from register file
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ocRnotWRam : out std_logic; --! r_notw to RAM
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ocLoadEn : out std_logic; --! safe result of alu
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ocEnableRAM : out std_logic; --! put akku on databus
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ocLoadInstr : out std_logic; --! load instruction control signal
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ocNextPC : out std_logic; --! increment pc
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ocAddrSel : out std_logic; --! pc on addressbus
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ocJump : out std_logic; --! do a ocJump
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ocPCregister : out std_logic; --! put PC to register File
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ocUsePC : out std_logic; --! use Register to fill in the PC
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ocLoad : out std_logic --! put databus to ALU immediate port
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);
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end component;
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component ControlUnit is
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port (
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iClk : in std_logic; --! iClk signal
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iReset : in std_logic; --! iReset signal
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icOpCode : in optype; --! icOpCode bus
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idCarry : in std_logic; --! carry from register file
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idZero : in std_logic; --! zero flag from register file
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ocRnotWRam : out std_logic; --! r_notw to RAM
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ocLoadEn : out std_logic; --! safe result of alu
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ocEnableRAM : out std_logic; --! put akku on databus
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ocLoadInstr : out std_logic; --! load instruction control signal
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ocNextPC : out std_logic; --! increment pc
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ocAddrSel : out std_logic; --! pc on addressbus
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ocJump : out std_logic; --! do a ocJump
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ocPCregister : out std_logic; --! put PC to register File
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ocUsePC : out std_logic; --! use Register to fill in the PC
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ocLoad : out std_logic --! put databus to ALU immediate port
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);
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end component;
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component RegFile is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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component RegFile is
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port(
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iClk : in std_logic;
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iReset : in std_logic;
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icRegAsel : in std_logic_vector(4 downto 0);
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icRegBsel : in std_logic_vector(4 downto 0);
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odRegA : out DATA;
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odRegB : out DATA;
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icRegAsel : in std_logic_vector(4 downto 0);
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icRegBsel : in std_logic_vector(4 downto 0);
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odRegA : out DATA;
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odRegB : out DATA;
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icPC : in std_logic; -- select PC as input to RegisterFile
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idPC : in DATA;
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icPC : in std_logic; -- select PC as input to RegisterFile
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idPC : in DATA;
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icRegINsel : in std_logic_vector(4 downto 0);
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icRegINsel: in std_logic_vector(4 downto 0);
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idDataIn : in DATA;
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idCarryIn : in std_logic;
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idZeroIn : in std_logic;
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idDataIn : in DATA;
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idCarryIn : in std_logic;
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idZeroIn : in std_logic;
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icLoadEn : in std_logic;
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icLoadEn : in std_logic;
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odCarryOut : out std_logic;
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odZeroOut : out std_logic
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);
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end component;
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odCarryOut: out std_logic;
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odZeroOut : out std_logic
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);
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end component;
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component ALU is
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Port(
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idOperand1 : in DATA;
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idOperand2 : in DATA;
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idImmidiate : in DATA;
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idCarryIn : in std_logic;
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component ALU is
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port(
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idOperand1 : in DATA;
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idOperand2 : in DATA;
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idImmidiate : in DATA;
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idCarryIn : in std_logic;
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odResult : out DATA;
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odCarryOut : out std_logic;
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odZeroOut : out std_logic;
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odResult : out DATA;
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odCarryOut : out std_logic;
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odZeroOut : out std_logic;
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icOperation : in OPTYPE
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);
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end component;
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icOperation : in OPTYPE
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);
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end component;
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component FetchDecode is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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component FetchDecode is
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port(
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iClk : in std_logic;
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iReset : in std_logic;
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idData : in DATA;
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icAddrSel : in std_logic;
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icLoadInstr : in std_logic;
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icJump : in std_logic;
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icNextPC : in std_logic;
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idPC : in ADDRESS;
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icUsePC : in std_logic;
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odPC : out ADDRESS;
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idData : in DATA;
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icAddrSel : in std_logic;
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icDecodeInstr : in std_logic;
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icJump : in std_logic;
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icNextPC : in std_logic;
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idPC : in ADDRESS;
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icUsePC : in std_logic;
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odPC : out ADDRESS;
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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odRegAsel : out std_logic_vector(4 downto 0);
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odRegBsel : out std_logic_vector(4 downto 0);
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odRegINsel : out std_logic_vector(4 downto 0);
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ocOperation : out OPTYPE
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);
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end component;
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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odRegAsel : out std_logic_vector(4 downto 0);
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odRegBsel : out std_logic_vector(4 downto 0);
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odRegINsel : out std_logic_vector(4 downto 0);
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ocOperation : out OPTYPE
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);
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end component;
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component MemInterface is
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Port(
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bdDataBus : inout DATA;
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odAddress : out ADDRESS;
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ocRnotW : out std_logic;
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ocEnable : out std_logic;
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component MemInterface is
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port(
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bdDataBus : inout DATA;
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odAddress : out ADDRESS;
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ocRnotW : out std_logic;
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ocEnable : out std_logic;
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icBusCtrlCPU : in std_logic;
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icRAMEnable : in std_logic;
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odDataOutCPU : out DATA;
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idDataInCPU : in DATA;
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idAddressCPU : in ADDRESS
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);
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end component;
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icBusCtrlCPU : in std_logic;
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icRAMEnable : in std_logic;
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odDataOutCPU : out DATA;
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idDataInCPU : in DATA;
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idAddressCPU : in ADDRESS
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);
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end component;
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signal sdPC : DATA;
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signal scPCregister : std_logic;
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signal sdPC : DATA;
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signal scPCregister : std_logic;
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signal scUsePC : std_logic;
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signal sdPCfetch : ADDRESS;
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signal scUsePC : std_logic;
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signal sdPCfetch : ADDRESS;
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signal scLoad : std_logic;
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signal scLoad : std_logic;
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signal scOpCode : optype;
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signal sdCarryRF : std_logic;
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signal sdZeroRF : std_logic;
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signal scRnotWRam : std_logic;
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signal scLoadEn : std_logic;
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signal scEnableRAM : std_logic;
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signal scLoadInstr : std_logic;
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signal scNextPC : std_logic;
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signal scAddrSel : std_logic;
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signal scJump : std_logic;
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signal sdAkkuRes : DATA;
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signal sdCarryAkku : std_logic;
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signal sdZeroAkku : std_logic;
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signal sdDataIn : DATA;
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signal sdAddress : ADDRESS;
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signal sdImmidiate : DATA;
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signal sdImmidiateALU: DATA;
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signal sdRegAsel : std_logic_vector(4 downto 0);
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signal sdRegBsel : std_logic_vector(4 downto 0);
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signal sdRegINsel : std_logic_vector(4 downto 0);
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signal sdRegA : DATA;
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signal sdRegB : DATA;
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signal scOpCode : optype;
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signal sdCarryRF : std_logic;
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signal sdZeroRF : std_logic;
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signal scRnotWRam : std_logic;
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signal scLoadEn : std_logic;
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signal scEnableRAM : std_logic;
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signal scLoadInstr : std_logic;
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signal scNextPC : std_logic;
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signal scAddrSel : std_logic;
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signal scJump : std_logic;
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signal sdAkkuRes : DATA;
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signal sdCarryAkku : std_logic;
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signal sdZeroAkku : std_logic;
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signal sdDataIn : DATA;
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signal sdAddress : ADDRESS;
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signal sdImmidiate : DATA;
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signal sdImmidiateALU : DATA;
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signal sdRegAsel : std_logic_vector(4 downto 0);
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signal sdRegBsel : std_logic_vector(4 downto 0);
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signal sdRegINsel : std_logic_vector(4 downto 0);
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signal sdRegA : DATA;
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signal sdRegB : DATA;
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begin
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SW : Steuerwerk PORT MAP (
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iClk => iClk,
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iReset => iReset,
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icOpCode => scOpCode,
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idCarry => sdCarryRF,
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idZero => sdZeroRF,
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ocRnotWRam => scRnotWRam,
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ocLoadEn => scLoadEn,
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ocEnableRAM => scEnableRAM,
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ocLoadInstr => scLoadInstr,
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ocNextPC => scNextPC,
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ocAddrSel => scAddrSel,
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ocJump => scJump,
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ocPCregister => scPCregister,
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ocUsePC => scUsePC,
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ocLoad => scLoad
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SW : ControlUnit port map (
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iClk => iClk,
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iReset => iReset,
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icOpCode => scOpCode,
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idCarry => sdCarryRF,
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idZero => sdZeroRF,
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ocRnotWRam => scRnotWRam,
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ocLoadEn => scLoadEn,
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ocEnableRAM => scEnableRAM,
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ocLoadInstr => scLoadInstr,
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ocNextPC => scNextPC,
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ocAddrSel => scAddrSel,
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ocJump => scJump,
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ocPCregister => scPCregister,
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ocUsePC => scUsePC,
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ocLoad => scLoad
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);
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RF: RegFile PORT MAP(
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iClk => iClk,
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iReset => iReset,
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RF : RegFile port map(
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iClk => iClk,
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iReset => iReset,
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icRegAsel => sdRegAsel,
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icRegBsel => sdRegBsel,
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icRegINsel => sdRegINsel,
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icRegAsel => sdRegAsel,
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icRegBsel => sdRegBsel,
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icRegINsel => sdRegINsel,
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icPC => scPCregister,
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idPC => sdPC,
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icPC => scPCregister,
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idPC => sdPC,
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idDataIn => sdAkkuRes,
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idCarryIn => sdCarryAkku,
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idZeroIn => sdZeroAkku,
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idDataIn => sdAkkuRes,
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idCarryIn => sdCarryAkku,
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idZeroIn => sdZeroAkku,
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icLoadEn => scLoadEn,
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icLoadEn => scLoadEn,
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odRegA => sdRegA,
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odRegB => sdRegB,
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odCarryOut => sdCarryRF,
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odZeroOut => sdZeroRF
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);
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odRegA => sdRegA,
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odRegB => sdRegB,
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odCarryOut => sdCarryRF,
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odZeroOut => sdZeroRF
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);
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Calc : ALU Port MAP(
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idOperand1 => sdRegA,
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idOperand2 => sdRegB,
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idImmidiate => sdImmidiateALU,
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idCarryIn => sdCarryRF,
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Calc : ALU port map(
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idOperand1 => sdRegA,
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idOperand2 => sdRegB,
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idImmidiate => sdImmidiateALU,
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idCarryIn => sdCarryRF,
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odResult => sdAkkuRes,
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odCarryOut => sdCarryAkku,
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odZeroOut => sdZeroAkku,
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odResult => sdAkkuRes,
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odCarryOut => sdCarryAkku,
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odZeroOut => sdZeroAkku,
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icOperation => scOpCode
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);
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icOperation => scOpCode
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);
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sdPC(31 downto 16) <= (others=>'0');
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FaD : FetchDecode PORT MAP(
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iClk => iClk,
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iReset => iReset,
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sdPC(31 downto 16) <= (others => '0');
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FaD : FetchDecode port map(
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iClk => iClk,
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iReset => iReset,
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idData => sdDataIn,
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icAddrSel => scAddrSel,
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icLoadInstr => scLoadInstr,
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icJump => scJump,
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icNextPC => scNextPC,
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idData => sdDataIn,
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icAddrSel => scAddrSel,
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icDecodeInstr => scLoadInstr,
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icJump => scJump,
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icNextPC => scNextPC,
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odPC => sdPC(15 downto 0),
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idPC => sdRegA(15 downto 0),
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icUsePC => scUsePC,
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odAddress => sdAddress,
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odImmidiate => sdImmidiate,
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odRegAsel => sdRegAsel,
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odRegBsel => sdRegBsel,
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odRegINsel => sdRegINsel,
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ocOperation => scOpCode
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);
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odPC => sdPC(15 downto 0),
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idPC => sdRegA(15 downto 0),
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icUsePC => scUsePC,
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odAddress => sdAddress,
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odImmidiate => sdImmidiate,
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odRegAsel => sdRegAsel,
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odRegBsel => sdRegBsel,
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odRegINsel => sdRegINsel,
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ocOperation => scOpCode
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);
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MemIF : MemInterface PORT MAP(
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bdDataBus => bdData,
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odAddress => odAddress,
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ocRnotW => ocRnotW,
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ocEnable => ocEnable,
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MemIF : MemInterface port map(
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bdDataBus => bdData,
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odAddress => odAddress,
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ocRnotW => ocRnotW,
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ocEnable => ocEnable,
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icBusCtrlCPU => scRnotWRam,
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icRAMEnable => scEnableRAM,
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odDataOutCPU => sdDataIn,
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idDataInCPU => sdRegA,
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idAddressCPU => sdAddress
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);
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icBusCtrlCPU => scRnotWRam,
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icRAMEnable => scEnableRAM,
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odDataOutCPU => sdDataIn,
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idDataInCPU => sdRegA,
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idAddressCPU => sdAddress
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);
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sdImmidiateALU <= bdData when scLoad='1' else
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sdImmidiateALU <= bdData when scLoad = '1' else
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sdImmidiate;
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end Behavioral;
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