FIX: license and author information, signal name changes
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src/CPU.vhd
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src/CPU.vhd
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@ -1,41 +1,27 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:51:48 05/11/2011
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-- Design Name:
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-- Module Name: CPU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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-------------------------------------------------------
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--! @file
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--! @brief CPU Core of the Simple Processor Core (Geraffel Processor)
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--! @author Dominik Meyer/ Marcel Eckert
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--! @email dmeyer@federationhq.de
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--! @licence GPLv2
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--! @date unknown
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-------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.all;
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library work;
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use work.cpupkg.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--! CPU Core of the Simple Processor Core (Geraffel Processor)
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--!
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--! This Code is based on a processor core used at the Helmut Schmidt University for
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--! educational purposes.
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--!
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entity CPU is
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Port(
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iClk : in std_logic;
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iReset : in std_logic;
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port(
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iClk : in std_logic; --! main system clock
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iReset : in std_logic; --! system active high reset
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bdData : inout DATA; --! connection to databus
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odAddress : out ADDRESS; --! connection to addressbus
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ocEnable : out std_logic; --! enable or disable RAM
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@ -44,7 +30,7 @@ entity CPU is
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end CPU;
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architecture Behavioral of CPU is
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component Steuerwerk is
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component ControlUnit is
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port (
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iClk : in std_logic; --! iClk signal
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iReset : in std_logic; --! iReset signal
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@ -65,7 +51,7 @@ architecture Behavioral of CPU is
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end component;
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component RegFile is
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Port(
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port(
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iClk : in std_logic;
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iReset : in std_logic;
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@ -91,7 +77,7 @@ architecture Behavioral of CPU is
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end component;
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component ALU is
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Port(
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port(
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idOperand1 : in DATA;
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idOperand2 : in DATA;
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idImmidiate : in DATA;
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@ -106,13 +92,13 @@ architecture Behavioral of CPU is
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end component;
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component FetchDecode is
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Port(
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port(
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iClk : in std_logic;
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iReset : in std_logic;
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idData : in DATA;
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icAddrSel : in std_logic;
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icLoadInstr : in std_logic;
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icDecodeInstr : in std_logic;
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icJump : in std_logic;
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icNextPC : in std_logic;
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idPC : in ADDRESS;
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@ -129,7 +115,7 @@ architecture Behavioral of CPU is
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end component;
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component MemInterface is
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Port(
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port(
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bdDataBus : inout DATA;
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odAddress : out ADDRESS;
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ocRnotW : out std_logic;
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@ -177,7 +163,7 @@ architecture Behavioral of CPU is
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begin
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SW : Steuerwerk PORT MAP (
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SW : ControlUnit port map (
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iClk => iClk,
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iReset => iReset,
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icOpCode => scOpCode,
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@ -195,7 +181,7 @@ begin
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ocLoad => scLoad
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);
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RF: RegFile PORT MAP(
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RF : RegFile port map(
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iClk => iClk,
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iReset => iReset,
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@ -218,7 +204,7 @@ begin
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odZeroOut => sdZeroRF
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);
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Calc : ALU Port MAP(
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Calc : ALU port map(
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idOperand1 => sdRegA,
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idOperand2 => sdRegB,
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idImmidiate => sdImmidiateALU,
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@ -233,13 +219,13 @@ begin
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sdPC(31 downto 16) <= (others => '0');
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FaD : FetchDecode PORT MAP(
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FaD : FetchDecode port map(
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iClk => iClk,
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iReset => iReset,
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idData => sdDataIn,
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icAddrSel => scAddrSel,
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icLoadInstr => scLoadInstr,
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icDecodeInstr => scLoadInstr,
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icJump => scJump,
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icNextPC => scNextPC,
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@ -254,7 +240,7 @@ begin
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ocOperation => scOpCode
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);
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MemIF : MemInterface PORT MAP(
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MemIF : MemInterface port map(
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bdDataBus => bdData,
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odAddress => odAddress,
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ocRnotW => ocRnotW,
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@ -272,4 +258,3 @@ begin
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sdImmidiate;
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end Behavioral;
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