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FIX: license and author information, signal name changes

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Dominik Meyer 2013-12-30 15:11:56 +01:00
parent 75dbc9f109
commit 69e1ffe919
1 changed files with 245 additions and 260 deletions
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src/CPU.vhd
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@ -1,41 +1,27 @@
---------------------------------------------------------------------------------- -------------------------------------------------------
-- Company: --! @file
-- Engineer: --! @brief CPU Core of the Simple Processor Core (Geraffel Processor)
-- --! @author Dominik Meyer/ Marcel Eckert
-- Create Date: 10:51:48 05/11/2011 --! @email dmeyer@federationhq.de
-- Design Name: --! @licence GPLv2
-- Module Name: CPU - Behavioral --! @date unknown
-- Project Name: -------------------------------------------------------
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.all;
library work; library work;
use work.cpupkg.all; use work.cpupkg.all;
-- Uncomment the following library declaration if using --! CPU Core of the Simple Processor Core (Geraffel Processor)
-- arithmetic functions with Signed or Unsigned values --!
--use IEEE.NUMERIC_STD.ALL; --! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
-- Uncomment the following library declaration if instantiating --!
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is entity CPU is
Port( port(
iClk : in std_logic; iClk : in std_logic; --! main system clock
iReset : in std_logic; iReset : in std_logic; --! system active high reset
bdData : inout DATA; --! connection to databus bdData : inout DATA; --! connection to databus
odAddress : out ADDRESS; --! connection to addressbus odAddress : out ADDRESS; --! connection to addressbus
ocEnable : out std_logic; --! enable or disable RAM ocEnable : out std_logic; --! enable or disable RAM
@ -44,7 +30,7 @@ entity CPU is
end CPU; end CPU;
architecture Behavioral of CPU is architecture Behavioral of CPU is
component Steuerwerk is component ControlUnit is
port ( port (
iClk : in std_logic; --! iClk signal iClk : in std_logic; --! iClk signal
iReset : in std_logic; --! iReset signal iReset : in std_logic; --! iReset signal
@ -65,7 +51,7 @@ architecture Behavioral of CPU is
end component; end component;
component RegFile is component RegFile is
Port( port(
iClk : in std_logic; iClk : in std_logic;
iReset : in std_logic; iReset : in std_logic;
@ -91,7 +77,7 @@ architecture Behavioral of CPU is
end component; end component;
component ALU is component ALU is
Port( port(
idOperand1 : in DATA; idOperand1 : in DATA;
idOperand2 : in DATA; idOperand2 : in DATA;
idImmidiate : in DATA; idImmidiate : in DATA;
@ -106,13 +92,13 @@ architecture Behavioral of CPU is
end component; end component;
component FetchDecode is component FetchDecode is
Port( port(
iClk : in std_logic; iClk : in std_logic;
iReset : in std_logic; iReset : in std_logic;
idData : in DATA; idData : in DATA;
icAddrSel : in std_logic; icAddrSel : in std_logic;
icLoadInstr : in std_logic; icDecodeInstr : in std_logic;
icJump : in std_logic; icJump : in std_logic;
icNextPC : in std_logic; icNextPC : in std_logic;
idPC : in ADDRESS; idPC : in ADDRESS;
@ -129,7 +115,7 @@ architecture Behavioral of CPU is
end component; end component;
component MemInterface is component MemInterface is
Port( port(
bdDataBus : inout DATA; bdDataBus : inout DATA;
odAddress : out ADDRESS; odAddress : out ADDRESS;
ocRnotW : out std_logic; ocRnotW : out std_logic;
@ -177,7 +163,7 @@ architecture Behavioral of CPU is
begin begin
SW : Steuerwerk PORT MAP ( SW : ControlUnit port map (
iClk => iClk, iClk => iClk,
iReset => iReset, iReset => iReset,
icOpCode => scOpCode, icOpCode => scOpCode,
@ -195,7 +181,7 @@ begin
ocLoad => scLoad ocLoad => scLoad
); );
RF: RegFile PORT MAP( RF : RegFile port map(
iClk => iClk, iClk => iClk,
iReset => iReset, iReset => iReset,
@ -218,7 +204,7 @@ begin
odZeroOut => sdZeroRF odZeroOut => sdZeroRF
); );
Calc : ALU Port MAP( Calc : ALU port map(
idOperand1 => sdRegA, idOperand1 => sdRegA,
idOperand2 => sdRegB, idOperand2 => sdRegB,
idImmidiate => sdImmidiateALU, idImmidiate => sdImmidiateALU,
@ -233,13 +219,13 @@ begin
sdPC(31 downto 16) <= (others => '0'); sdPC(31 downto 16) <= (others => '0');
FaD : FetchDecode PORT MAP( FaD : FetchDecode port map(
iClk => iClk, iClk => iClk,
iReset => iReset, iReset => iReset,
idData => sdDataIn, idData => sdDataIn,
icAddrSel => scAddrSel, icAddrSel => scAddrSel,
icLoadInstr => scLoadInstr, icDecodeInstr => scLoadInstr,
icJump => scJump, icJump => scJump,
icNextPC => scNextPC, icNextPC => scNextPC,
@ -254,7 +240,7 @@ begin
ocOperation => scOpCode ocOperation => scOpCode
); );
MemIF : MemInterface PORT MAP( MemIF : MemInterface port map(
bdDataBus => bdData, bdDataBus => bdData,
odAddress => odAddress, odAddress => odAddress,
ocRnotW => ocRnotW, ocRnotW => ocRnotW,
@ -272,4 +258,3 @@ begin
sdImmidiate; sdImmidiate;
end Behavioral; end Behavioral;