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@INPROCEEDINGS{path_delay_measurement,
author={Ruffoni, M. and Bogliolo, A.},
booktitle={Signal Propagation on Interconnects, 6th IEEE Workshop on. Proceedings}, title={Direct Measures of Path Delays on Commercial FPGA Chips},
year={2002},
month={may},
volume={},
number={},
pages={157 -159},
keywords={Field programmable gate arrays;Frequency;Inverters;Propagation delay;Ring oscillators;Routing;Semiconductor device measurement;Testing;Timing;Wire;},
}
@INPROCEEDINGS{pdm:vdl,
author={Chan, AH. and Roberts, G.W.},
booktitle={Test Conference, 2001. Proceedings. International},
title={A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line},
year={2001},
month={},
pages={858-867},
keywords={CMOS logic circuits;application specific integrated circuits;calibration;delay lines;electric variables measurement;field programmable gate arrays;integrated circuit testing;logic testing;timing;CMOS process;IC prototype;RTL description;calibration;component-invariant technique;differential nonlinearity timing errors;high-resolution timing measurement device;production test;register transfer level description;test time;vernier delay line technique;Circuit testing;Clocks;Counting circuits;Delay lines;Field programmable gate arrays;Performance evaluation;Phase measurement;Propagation delay;Ring oscillators;Timing jitter},
}
@article{pdm:selfmeasurement,
author = {Wong, Justin S. J. and Sedcole, Pete and Cheung, Peter Y. K.},
title = {Self-Measurement of Combinatorial Circuit Delays in FPGAs},
journal = {ACM Trans. Reconfigurable Technol. Syst.},
issue_date = {June 2009},
volume = {2},
number = {2},
month = jun,
year = {2009},
pages = {10:1--10:22},
articleno = {10},
numpages = {22},
acmid = {1534920},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {FPGA, Testing, configuration, delay measurement},
}
@INPROCEEDINGS{pdm:ro0,
author={Stanciu, A and Craciun, A},
booktitle={Optimization of Electrical and Electronic Equipment (OPTIM), 2014 International Conference on},
title={Generating an unique identifier for FPGA devices},
year={2014},
month={May},
pages={802-808},
keywords={BCH codes;error correction codes;error detection codes;field programmable gate arrays;logic design;oscillators;FPGA designs;FPGA devices;FPGA security technique;IP vendor;RO security;building automation;complex factories;control systems;cost reduction;device prototyping;digital circuits;electronic devices;hardware attacks;manufacturing flow;medical apparatus;motor controllers;ring oscillators;security issues;switches;system integrator;Encoding;Field programmable gate arrays;Generators;Hardware;Manufacturing;Ring oscillators},
}
@INPROCEEDINGS{pdm:ro1,
author={Jiliang Zhang and Qiang Wu and Yongqiang Lyu and Qiang Zhou and Yici Cai and Yaping Lin and Gang Qu},
booktitle={Computer-Aided Design and Computer Graphics (CAD/Graphics), 2013 International Conference on},
title={Design and Implementation of a Delay-Based PUF for FPGA IP Protection},
year={2013},
month={Nov},
pages={107-114},
keywords={copy protection;delays;digital rights management;field programmable gate arrays;industrial property;logic design;oscillators;Anderson PUF;FPGA IP protection;RO based PUF;arbiter-based PUF;challenge-response pairs;delay-based PUF;digital rights management;field programmable gate arrays;hard macros;intellectual property;key generation;physical unclonable function;resource overhead;ring oscillator;uncontrollable process variations;Delays;Fabrication;Field programmable gate arrays;Multiplexing;Random access memory;Shift registers;Table lookup;EDA;FPGAs;IP cores;fabrication variation;fingerprint;hardware security;intellectual property (IP) protection;physical unclonable functions (PUFs);watermarking},
}
@INPROCEEDINGS{pdm:routing,
author={Zhua, K. and Yao-Wen Chang and Wong, D. F.},
booktitle={Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on},
title={Timing-driven routing for symmetrical-array-based FPGAs},
year={1998},
month={Oct},
pages={628-633},
keywords={circuit layout CAD;field programmable gate arrays;logic CAD;network routing;timing;FPGA;FPGAs;benchmark circuits;complexity;delay;routing resources;symmetrical-array-based;timing-driven global router;timing-driven routing trees;wirelength;Approximation algorithms;Circuit optimization;Delay;Field programmable gate arrays;Information science;Integrated circuit interconnections;Logic arrays;Routing;Switches;Timing},
}
@ARTICLE{pdm:routing1,
author={Alexander, M.J. and Robins, G.},
journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
title={New performance-driven FPGA routing algorithms},
year={1996},
month={Dec},
volume={15},
number={12},
pages={1505-1517},
keywords={VLSI;circuit layout CAD;delays;field programmable gate arrays;integrated circuit design;logic CAD;logic partitioning;network routing;trees (mathematics);FPGA;Steiner algorithms;Steiner tree constructions;Xilinx parts;arborescence algorithms;channel width;optimal source-sink pathlengths;performance bounds;routing algorithms;routing solutions;wirelength;Algorithm design and analysis;Circuit simulation;Computer science;Construction industry;Field programmable gate arrays;Flexible printed circuits;Propagation delay;Routing;Steiner trees;Very large scale integration},
}
@INPROCEEDINGS{pdm:ro1,
author={Jiliang Zhang and Qiang Wu and Yongqiang Lyu and Qiang Zhou and Yici Cai and Yaping Lin and Gang Qu},
booktitle={Computer-Aided Design and Computer Graphics (CAD/Graphics), 2013 International Conference on},
title={Design and Implementation of a Delay-Based PUF for FPGA IP Protection},
year={2013},
month={Nov},
pages={107-114},
keywords={copy protection;delays;digital rights management;field programmable gate arrays;industrial property;logic design;oscillators;Anderson PUF;FPGA IP protection;RO based PUF;arbiter-based PUF;challenge-response pairs;delay-based PUF;digital rights management;field programmable gate arrays;hard macros;intellectual property;key generation;physical unclonable function;resource overhead;ring oscillator;uncontrollable process variations;Delays;Fabrication;Field programmable gate arrays;Multiplexing;Random access memory;Shift registers;Table lookup;EDA;FPGAs;IP cores;fabrication variation;fingerprint;hardware security;intellectual property (IP) protection;physical unclonable functions (PUFs);watermarking},
}