ADD: added some bibliography

os.bib

@@ -0,0 +1,39 @@
+@incollection{os:reconos,
+  title={Reconos: An operating system for dynamically reconfigurable hardware},
+  author={L{\"u}bbers, Enno and Platzner, Marco},
+  booktitle={Dynamically Reconfigurable Systems},
+  pages={269--290},
+  year={2010},
+  publisher={Springer}
+}
+
+@article{os:embedded,
+  title={Embedded Linux platform for data acquisition systems},
+  author={Patel, Jigneshkumar J and Reddy, Nagaraj and Kumari, Praveena and Rajpal, Rachana and Pujara, Harshad and Jha, R and Kalappurakkal, Praveen},
+  journal={Fusion Engineering and Design},
+  volume={89},
+  number={5},
+  pages={684--688},
+  year={2014},
+  publisher={Elsevier}
+}
+
+@article{os:r3tos,
+  title={R3TOS: a novel reliable reconfigurable real-time operating system for highly adaptive, efficient, and dependable computing on FPGAs},
+  author={Iturbe, Xabier and Benkrid, Khaled and Hong, Chuan and Ebrahim, Ali and Torrego, Raul and Martinez, Israel and Arslan, Tughrul and Perez, JM},
+  journal={Computers, IEEE Transactions on},
+  volume={62},
+  number={8},
+  pages={1542--1556},
+  year={2013},
+  publisher={IEEE}
+}
+
+@inproceedings{os:capos,
+  title={CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures},
+  author={G{\"o}hringer, Diana and H{\"u}bner, Michael and Zeutebouo, Etienne Nguepi and Becker, J{\"u}rgen},
+  booktitle={Parallel \& Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on},
+  pages={1--8},
+  year={2010},
+  organization={IEEE}
+}

publications_dmeyer.bib

@@ -17,6 +17,16 @@
  address = {New York, NY, USA},
 }
 
+@phdthesis{Meyer2,
+    author = {Dominik Meyer},
+    title = {Multicore Reconfiguration Platform - A Research and Evaluation
+FPGA Framework for Runtime Reconfigurable Systems},
+    school = {Helmut-Schmidt-Universität },
+    year = {2015},
+    address = {Holstenhofweg 85, 22043 Hamburg},
+    language = {eng},
+}
+
 @Unpublished{Meyer1,
   author = 	 {Meyer, Dominik and Haase, Jan and Eckert, Marcel and Klauer, Bernd},
   title = 	 {Clock Speed Optimization of Partial Runtime Reconfigurable Systems by Signal Latency Measurement},

standards.bib

@@ -0,0 +1,8 @@
+@ARTICLE{jtag,
+journal={IEEE Std 1149.1-2001},
+title={IEEE Standard Test Access Port and Boundary Scan Architecture},
+year={2001},
+month={July},
+pages={1-212},
+keywords={BSDL;Boundary-Scan Description Language;JTAG;TAP;VHDL;VHSIC Hardware Description Language;boundary scan;boundary-scan architecture;boundary-scan register;circuit boards;circuitry;integrated circuit;printed circuit boards;test;test access port},
+doi={10.1109/IEEESTD.2001.92950},}