99 lines
3.0 KiB
TeX
99 lines
3.0 KiB
TeX
|
%
|
||
|
% Technische Informatik
|
||
|
\newacronym[
|
||
|
description=Application Specific Standard Product
|
||
|
]{assp}{ASSP}{application specific standard product}
|
||
|
\newacronym[
|
||
|
description=Application Specific Integrated Circuit
|
||
|
]{asic}{ASIC}{application specific integrated circuit}
|
||
|
\newacronym[
|
||
|
description=Configurable Logic Block
|
||
|
]{clb}{CLB}{configurable logic block}
|
||
|
\newacronym[
|
||
|
description=Complementary Metal-Oxide-Semiconductor
|
||
|
]{cmos}{CMOS}{complementary metal-oxide-semiconductor}
|
||
|
\newacronym[
|
||
|
description=Complex Programmable Logic Device
|
||
|
]{cpld}{CPLD}{complex programmable logic device}
|
||
|
\newacronym[
|
||
|
description=Erasable Programmable Read Only Memory
|
||
|
]{eprom}{EPROM}{erasable programmable read only memory}
|
||
|
\newacronym[
|
||
|
description=Electrically Erasable Programmable Read Only Memory
|
||
|
]{eeprom}{EEPROM}{electrically erasable programmable read only memory}
|
||
|
\newacronym[
|
||
|
description=Field Programmable Gate Array
|
||
|
]{fpga}{FPGA}{field programmable gate array}
|
||
|
\newacronym[
|
||
|
description=Generic Array of Logic
|
||
|
]{gal}{GAL}{generic array of logic}
|
||
|
\newacronym[
|
||
|
description=Hardware Description Language
|
||
|
]{hdl}{HDL}{hardware description language}
|
||
|
\newacronym[
|
||
|
description=Integrated Circuit
|
||
|
]{ic}{IC}{integrated circuit}
|
||
|
\newacronym[
|
||
|
description=Input/Output
|
||
|
]{io}{I/O}{input/output}
|
||
|
\newacronym[
|
||
|
description=Look-Up-Table
|
||
|
]{lut}{LUT}{look-up-table}
|
||
|
\newacronym[
|
||
|
description=Microcontroller
|
||
|
]{mcu}{MCU}{microcontroller}
|
||
|
\newacronym[
|
||
|
description=One-Time-Programmable
|
||
|
]{otp}{OTP}{one-time-programmable}
|
||
|
\newacronym[
|
||
|
description=Programmable Array Logic
|
||
|
]{pal}{PAL}{programmable array logic}
|
||
|
\newacronym[
|
||
|
description=Programmable Logic Arrays
|
||
|
]{pla}{PLA}{programmable logic arrays}
|
||
|
\newacronym[
|
||
|
description=Programmable Logic Device
|
||
|
]{pld}{PLD}{programmable logic device}
|
||
|
\newacronym[
|
||
|
description=Programmable Read Only Memory
|
||
|
]{prom}{PROM}{programmable read only memory}
|
||
|
\newacronym[
|
||
|
description=Simple Programmable Logic Device
|
||
|
]{spld}{SPLD}{simple programmable logic device}
|
||
|
\newacronym[
|
||
|
description=Static Random-Access Memory
|
||
|
]{sram}{SRAM}{static random-access memory}
|
||
|
\newacronym[
|
||
|
description=Very High Speed Integrated Circuit HDL
|
||
|
]{vhdl}{VHDL}{very high speed integrated circuit HDL}
|
||
|
%
|
||
|
% Mechatronik
|
||
|
\newacronym[
|
||
|
description=Analog-to-Digital Converter
|
||
|
]{adc}{ADC}{analog-to-digital converter}
|
||
|
\newacronym[
|
||
|
description=Active Noise Control
|
||
|
]{anc}{ANC}{active noise control}
|
||
|
\newacronym[
|
||
|
description=Digital-to-Analog Converter
|
||
|
]{dac}{DAC}{digital-to-analog converter}
|
||
|
\newacronym[
|
||
|
description=Digital Signal Processing
|
||
|
]{dsp}{DSP}{digital signal processing}
|
||
|
\newacronym[
|
||
|
description=Finite Impulse Response
|
||
|
]{fir}{FIR}{finite impulse response}
|
||
|
\newacronym[
|
||
|
description=Infinite Impulse Response
|
||
|
]{iir}{IIR}{infinite impulse response}
|
||
|
\newacronym[
|
||
|
description=Multiple-Input and Multiple-Output
|
||
|
]{mimo}{MIMO}{multiple-input and multiple-output}
|
||
|
\newacronym[
|
||
|
description=Filtered-x LMS
|
||
|
]{fxlms}{FXLMS}{filtered-x LMS}
|
||
|
\newacronym[
|
||
|
description=Least Mean Square
|
||
|
]{lms}{LMS}{least mean square}
|
||
|
% Wirtschaft
|