207 lines
6.6 KiB
VHDL
207 lines
6.6 KiB
VHDL
--------------------------------------------------------------------------------
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-- Entity: SenderAndFifo
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--------------------------------------------------------------------------------
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-- Copyright ... 2011
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-- Filename : SenderAndFifo.vhd
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-- Creation date : 2011-05-31
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-- Author(s) : marcel
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-- Version : 1.00
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-- Description : implements an RS232 Sender with additional Fifo
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--------------------------------------------------------------------------------
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-- File History:
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-- Date Version Author Comment
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-- 2011-05-31 1.00 marcel Creation of File
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--------------------------------------------------------------------------------
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--! brief
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--! implements an RS232 Sender with additional Fifo
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--! detailed
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--! implements an RS232 Sender with additonal Fifo (8 Bit data width, 4k data depth)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity SenderAndFifo is
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port (
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iSysClk : in std_logic; --! signal description System side clock
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ieClkEn : in std_logic;
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ieBaudClkEn : in std_logic; --! signal description UART clock (BAUD Rate frequency!)
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iReset : in std_logic; --! signal description asynchronous reset
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icSend : in std_logic; --! signal description add data <idDataSend> to Fifo (Enable Signal)
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idDataSend : in std_logic_vector(7 downto 0); --! signal description data to be added to the Fifo
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idParity : in std_logic; --! signal description the parity bit for the data
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icEnableParity: in std_logic; --! signal description enable the sending of the parity bit
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ocSEmpty : out std_logic; --! signal description indicates that Fifo is empty
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ocSFull : out std_logic; --! signal description indicates that Fifo is full
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ocSAlmostE : out std_logic; --! signal description indicates that Fifo is empty to half full
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ocSAlmostF : out std_logic; --! signal description indicates that Fifo is half full to full
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odTransmit : out std_logic --! signal description signal for the RS232 Tx line
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);
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end SenderAndFifo;
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architecture arch of SenderAndFifo is
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component Sender is
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port (
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iSysClk : in std_logic;
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ieBaudClkEn : in std_logic;
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iReset : in STD_LOGIC;
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icSend : in STD_LOGIC;
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idData : in STD_LOGIC_VECTOR (7 downto 0);
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idParity : in std_logic;
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icEnableParity:in std_logic;
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odTransmit : out STD_LOGIC;
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ocReady : out STD_LOGIC;
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ocSyn : out STD_LOGIC);
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end component;
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component SimpleFifo is
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generic (
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GEN_WIDTH : integer := 9; --! Data width of each data word
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GEN_DEPTH : integer := 256; --! how many values can be stored in Fifo
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GEN_A_EMPTY : integer := 2; --! when is the FIFO signaled as almost empty
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GEN_A_FULL : integer := 250 --! when is the FIFO signaled as almost full
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);
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port (
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icWriteClk : in std_logic;
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icWe : in std_logic;
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icReadClk : in std_logic;
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icReadEnable : in std_logic;
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idData : in std_logic_vector(8 downto 0);
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odData : out std_logic_vector(8 downto 0);
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ocEmpty : out std_logic;
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ocFull : out std_logic;
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ocAempty : out std_logic;
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ocAfull : out std_logic;
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icClkEnable : in std_logic; --! active high clock enable signal
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icReset : in std_logic
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);
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end component;
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signal scSenderRead : std_logic;
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signal scSenderReadEn : std_logic;
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signal sdDataToSend : STD_LOGIC_VECTOR (8 downto 0);
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signal scSenderEmpty : std_logic;
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signal scSenderFull : std_logic;
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signal scSenderAEmpty : std_logic;
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signal scSenderAFull : std_logic;
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signal scSenderReady : std_logic;
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signal scSenderSendReq : std_logic;
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signal scSyn : std_logic;
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type SenderCtrlType is (SENDER_WAITING, SENDER_SEND, SENDER_SENDING, SENDER_SENDING_SYN);
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signal sSenderCtrlState : SenderCtrlType;
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signal seSend : std_logic;
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signal sdFifoDataIn : std_logic_vector(8 downto 0);
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begin
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scSenderReadEn <= scSenderRead and ieBaudClkEn;
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seSend <= icSend and ieClkEn;
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sendFifo : SimpleFifo
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PORT MAP(
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icReset => iReset,
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icWriteClk => iSysClk,
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icWe => seSend,
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icReadClk => iSysClk,
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icReadEnable => scSenderReadEn,
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idData => sdFifoDataIn,
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odData => sdDataToSend,
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ocEmpty => scSenderEmpty,
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ocFull => scSenderFull,
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ocAempty => scSenderAEmpty,
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ocAfull => scSenderAFull,
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icClkEnable => ieClkEn
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);
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sdFifoDataIn <= idDataSend & idParity;
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ocSEmpty <= scSenderEmpty;
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ocSFull <= scSenderFull;
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ocSAlmostE <= scSenderAEmpty;
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ocSAlmostF <= scSenderAFull;
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RS232Sender : Sender
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PORT MAP(
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iSysClk => iSysClk,
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ieBaudClkEn => ieBaudClkEn,
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iReset => iReset,
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icSend => scSenderSendReq,
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idData => sdDataToSend(8 downto 1),
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idParity => sdDataToSend(0),
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icEnableParity=>icEnableParity,
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odTransmit => odTransmit,
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ocReady => scSenderReady,
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ocSyn => scSyn
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);
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SenderCtrl : process (iSysClk, iReset, sSenderCtrlState, scSenderReady, ieclken, scsenderempty, scsyn)
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begin
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if (rising_edge(iSysClk)) then
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if (iReset = '1') then
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sSenderCtrlState <= SENDER_WAITING;
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elsif ieClkEn = '1' then
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case sSenderCtrlState is
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when SENDER_WAITING =>
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if scSenderEmpty = '0' then
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sSenderCtrlState <= SENDER_SEND;
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end if;
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when SENDER_SEND =>
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if scSenderReady = '0' then
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sSenderCtrlState <= SENDER_SENDING;
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end if;
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when SENDER_SENDING =>
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if scSyn = '1' then
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sSenderCtrlState <= SENDER_SENDING_SYN;
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end if;
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when SENDER_SENDING_SYN =>
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if scSyn = '0' then
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sSenderCtrlState <= SENDER_WAITING;
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end if;
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end case;
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end if;
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end if;
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scSenderRead <= '0';
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scSenderSendReq <= '0';
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if (sSenderCtrlState = SENDER_SEND) then
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scSenderSendReq <= '1';
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end if;
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if (sSenderCtrlState = SENDER_SENDING_SYN) then
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scSenderRead <= '1';
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end if;
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end process;
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end arch;
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