60 lines
1.2 KiB
VHDL
60 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.cpupkg.all;
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entity top is
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generic(
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GEN_SYS_CLK : integer := 50000000; --! system clock in HZ
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GEN_SOC_CLK : integer := 5000000 --! soc clock in HZ
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);
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port( icclk : in std_logic; -- Taktsignal
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icreset : in std_logic; -- Resetsignal
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odLED : out std_logic_vector(7 downto 0);
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odRS232 : out std_logic;
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idRS232 : in std_logic
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);
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end top;
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architecture arch of top is
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component SOC
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generic (
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GEN_SYS_CLK : integer;
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GEN_SOC_CLK : integer
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);
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port (
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icclk : in std_logic;
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icreset : in std_logic;
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odLED : out std_logic_vector ( 7 downto 0 );
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odRS232 : out std_logic;
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idRS232 : in std_logic
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);
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end component;
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signal scClk : std_logic;
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begin
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soc0:entity work.SOC
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generic map(
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GEN_SYS_CLK => 50000000,
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GEN_SOC_CLK => 5000000
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)
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port map(
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icclk => icclk,
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icreset => icreset,
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odLED => odLED,
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odRS232 => odRS232,
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idRS232 => idRS232
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);
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end arch;
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