73 lines
2.1 KiB
VHDL
73 lines
2.1 KiB
VHDL
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-- Entity: clkDivider
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--------------------------------------------------------------------------------
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-- Copyright ... 2011
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-- Filename : clkDivider.vhd
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-- Creation date : 2011-05-25
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-- Author(s) : marcel
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-- Version : 1.00
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-- Description : generates a clock frequency <GEN_FreqOut_Hz> based on
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-- input freuency <GEN_FreqOut_Hz>
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-- Attention: avoid "strange" samples as 3:2
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--------------------------------------------------------------------------------
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-- File History:
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-- Date Version Author Comment
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-- unknown 0.10 marcel Creation of File
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-- 2011-05-25 1.00 marcel GENERICs added
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--! brief
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--! generates a clock frequency <GEN_FreqOut_Hz> based on
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--! input freuency <GEN_FreqOut_Hz>
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--! Generics can also be used to define ratio (like 4 (IN) : 1(Out))
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--! Attention: avoid "strange" ratios (like 3:2)
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--! detailed
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--! see brief
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entity clkDivider is
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generic(
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GEN_FreqIn_Hz : integer := 200000000; --! signal description input clock frequency in Hz for <iClk_in>
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GEN_FreqOut_Hz : integer := 100000000 --! signal description output clock frequency in Hz for <oClk_out>
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);
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port (
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iClk_in : in STD_LOGIC; --! signal description input clock
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iReset : in STD_LOGIC; --! signal description asynchronous reset (can be tied to '0')
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oClk_out : out STD_LOGIC --! signal description output clock
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);
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end clkDivider;
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architecture Behavioral of clkDivider is
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constant cLimit : integer := GEN_FreqIn_Hz / (2 * GEN_FreqOut_Hz);
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signal sCounter : integer := 0;
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signal sClk_out : STD_LOGIC := '0';
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begin
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process (iClk_in, iReset)
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begin
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if (iReset = '1') then
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sCounter <= 0;
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sClk_out <= '0';
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elsif (rising_edge(iClk_in)) then
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if (sCounter = (cLimit-1)) then
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sCounter <= 0;
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sClk_out <= not sClk_out;
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else
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sCounter <= sCounter + 1;
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end if;
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end if;
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end process;
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oClk_out <= sClk_out;
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end Behavioral;
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