129 lines
4.2 KiB
VHDL
129 lines
4.2 KiB
VHDL
-------------------------------------------------------
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--! @file
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--! @brief simple RAM for the IIB2 Akkumulator machine
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--! @author Dominik Meyer
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--! @email dmeyer@hsu-hh.de
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--! @date 2010-11-18
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-------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library work;
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use work.cpupkg.all;
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--! simple RAM for the IIB2 Akkumulator machine using word addressing
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entity RAM is
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port (
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iClk : in std_logic;
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iReset : in std_logic;
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bdData : inout DATA; --! connection to databus
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idAddress : in ADDRESS; --! connection to addressbus
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icEnable : in std_logic; --! enable or disable RAM
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icRnotW : in std_logic --! read/write control
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);
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end RAM;
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architecture arch of RAM is
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type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
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signal sRAM : MEMORY := ( --! 4k * 32bit of RAM
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0 => B"00001100001000000000000011001000", --loa $1, 200
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1 => B"01000011111000000000000000001101", --jmc print
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2 => B"00001100001000000000000011001001", --loa $1, 201
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3 => B"01000011111000000000000000001101", --jmc print
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4 => B"00001100001000000000000011001010", --loa $1, 202
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5 => B"01000011111000000000000000001101", --jmc print
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6 => B"00001100001000000000000011001011", --loa $1, 203
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7 => B"01000011111000000000000000001101", --jmc print
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8 => B"00001100001000000000000011001100", --loa $1, 204
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9 => B"01000011111000000000000000001101", --jmc print
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10 => B"00111100001000000000001000000000", --lui $1, 512
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11 => B"01000011111000000000000000011010", --jmc printAscii
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12 => B"11111100000000000000000000000000", --hlt
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13 => B"00010010100000010000000000000000", --add $20, $1, $0
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14 => B"00001000000101001111111111110001", --sto $20, 65521
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15 => B"00000110100101000000000000000000", --shr $20, $20, $0
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16 => B"00000110100101000000000000000000", --shr $20, $20, $0
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17 => B"00000110100101000000000000000000", --shr $20, $20, $0
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18 => B"00000110100101000000000000000000", --shr $20, $20, $0
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19 => B"00000110100101000000000000000000", --shr $20, $20, $0
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20 => B"00000110100101000000000000000000", --shr $20, $20, $0
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21 => B"00000110100101000000000000000000", --shr $20, $20, $0
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22 => B"00000110100101000000000000000000", --shr $20, $20, $0
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23 => B"00110000000000000000000000011001", --jpz endPrint
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24 => B"00111000000000000000000000001110", --jmp printLoop
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25 => B"01000100000111110000000000000000", --ret
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26 => B"00010010100000010000000000000000", --add $20, $1, $0
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27 => B"00100110101101000111100000000000", --and $21, $20, 15
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28 => B"00100010101101011000000000000000", --or $21, $21, 48
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29 => B"00010110110101010101000000000000", --sub $22, $21, 10
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30 => B"00110100000000000000000000100000", --jpc smaller
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31 => B"00010010101101010011100000000000", --add $21, $21, 7
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32 => B"00001000000101011111111111110001", --sto $21, 65521
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33 => B"00000110100101000000000000000000", --shr $20, $20, $0
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34 => B"00000110100101000000000000000000", --shr $20, $20, $0
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35 => B"00000110100101000000000000000000", --shr $20, $20, $0
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36 => B"00000110100101000000000000000000", --shr $20, $20, $0
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37 => B"00110000000000000000000000000000", --jpz asciloop:
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38 => B"01000100000111110000000000000000", --ret
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--
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-- Some variables
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--
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-- Geraffel
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200 => x"61726547",
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201 => x"6c656666",
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-- Processor
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202 => x"6f725020",
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203 => x"73736563",
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204 => x"0a20726f",
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-- Return
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205 => x"0a202020",
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others => (others => '0')
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);
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signal tData : DATA;
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begin
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--! functionality of the RAM
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process(iClk, iReset)
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begin
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if (iReset = '1') then
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tData <= (others => '0');
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elsif (rising_edge(iClk)) then
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if (icEnable = '1') then
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if (icRnotW = '0') then
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sRam(conv_integer(unsigned(idAddress))) <= bdData;
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else
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tData <= sRam(conv_integer(unsigned(idAddress)));
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end if;
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end if;
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end if;
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end process;
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bdData <= tData when icRnotW = '1' and icEnable='1' else
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(others => 'Z');
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end arch;
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