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SimpleProcessorCore
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SimpleProcessorCore/src/Modules/UART
History
Dominik Meyer 5cbcbdd04f FIX: fixed wrong instantiation of SimpleFiFo 2014-02-08 21:42:33 +01:00
..
License ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
Makefile.files ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
README ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
Receiver.vhd ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
ReceiverAndFifo.vhd FIX: fixed wrong instantiation of SimpleFiFo 2014-02-08 21:42:33 +01:00
Sender.vhd ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00
SenderAndFifo.vhd FIX: fixed wrong instantiation of SimpleFiFo 2014-02-08 21:42:33 +01:00
UART.vhd ADD: switched to a fork of the used UART 2014-01-05 03:14:50 +01:00

README 

    Uart Component
---------------------

Component is a fork of the UART Component written by Marcel Eckert marcel.eckert@hsu-hh.de
at the Helmut Schmidt University in Hamburg.

The main difference at the moment is the usage of the SimpleFifo Component as Fifos
not multiple Implementations for different FPGAs.