SimpleProcessorCore

History

Dominik Meyer dbd8ef11a1 ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs		2014-01-05 02:52:21 +01:00
..
src	ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs	2014-01-05 02:52:21 +01:00
License	ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs	2014-01-05 02:52:21 +01:00
Makefile.files	ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs	2014-01-05 02:52:21 +01:00
README	ADD: Module for a Simple Fifo, later used in the UART, to get it running on all FPGAs	2014-01-05 02:52:21 +01:00

README

    Simple Fifo
--------------------


Simple Fifo is a VHDL Module implementing a very simple Fifo with 
configurable datawidth and depth...

It uses a self written clock domain crossing component and a dual port block ram module.

If you find bugs in these components, please fix them and send a pull request to
dmeyer@federationhq.de.