64 lines
1.4 KiB
VHDL
64 lines
1.4 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:03:34 05/11/2011
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-- Design Name:
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-- Module Name: MemInterface - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library work;
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use work.cpupkg.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity MemInterface is
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Port(
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bdDataBus : inout DATA;
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odAddress : out ADDRESS;
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ocRnotW : out std_logic;
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ocEnable : out std_logic;
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icBusCtrlCPU : in std_logic;
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icRAMEnable : in std_logic;
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odDataOutCPU : out DATA;
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idDataInCPU : in DATA;
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idAddressCPU : in ADDRESS
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);
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end MemInterface;
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architecture Behavioral of MemInterface is
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begin
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ocRnotW <= icBusCtrlCPU;
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odAddress <= idAddressCPU when icRAMEnable='1' else (others=>'0');
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ocEnable <= icRAMEnable;
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odDataOutCPU <= bdDataBus;
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bdDataBus <= idDataInCPU when icBusCtrlCPU = '0' else
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(others => 'Z');
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end Behavioral;
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