FIX: fixed some bugs
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ea4ab47f79
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17
asm/fib.s
Normal file
17
asm/fib.s
Normal file
@ -0,0 +1,17 @@
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lui $1, 1 # for sub 1
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lui $2, 1 # a
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lui $3, 1 # b
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lui $4, 1 # c
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lui $5, 33 # i
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lui $6, 2
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sub $5,$5,$6
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loop:
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add $3,$0,$2 # b=a
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add $2,$0,$4 # a=c
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add $4,$2,$3 # c=a+b
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sto $4, 5000
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sub $5,$5,$1 # $i--
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jpz end
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jmp loop
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end:
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hlt
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@ -9,4 +9,5 @@ sub $5, $5, $4
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jpz end
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jpz end
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jmp loop
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jmp loop
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end:
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end:
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sto $3, 5000
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hlt
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hlt
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@ -387,7 +387,10 @@ for my $i (@instructions) {
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for my $i (@instructions) {
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for my $i (@instructions) {
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if ($ARGV[1] eq "-vhdl") {
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if ($ARGV[1] eq "-vhdl") {
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printf("%4s \t => B\"%.32b\", --%s\n ",$i->{addr}, $i->{opc}, $i->{comment});
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printf("%4s \t => B\"%.32b\", --%s\n ",$i->{addr}, $i->{opc}, $i->{comment});
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} else {
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}
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elsif($ARGV[1] eq "-raw") {
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printf("%.32b\n",$i->{opc});
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}else {
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printf( "%4s %.32b #%s\n", $i->{addr}, $i->{opc}, $i->{comment} );
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printf( "%4s %.32b #%s\n", $i->{addr}, $i->{opc}, $i->{comment} );
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}
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}
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}
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}
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@ -39,7 +39,7 @@ architecture arch of top is
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signal scReset : std_logic;
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signal scReset : std_logic;
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begin
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begin
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scReset <= not icReset;
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scReset <= not icReset_n;
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soc0:entity work.SOC
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soc0:entity work.SOC
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generic map(
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generic map(
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