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If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/src/Modules/SimpleFifo/Makefile.files b/src/Modules/SimpleFifo/Makefile.files new file mode 100644 index 0000000..2bd1d5c --- /dev/null +++ b/src/Modules/SimpleFifo/Makefile.files @@ -0,0 +1,3 @@ +VHDL_PKG += +VHDL_TB += +VHDL_SRC += src/CDC_fifoIF.vhd src/dual_port_block_ram.vhd src/SimpleFifo.vhd \ No newline at end of file diff --git a/src/Modules/SimpleFifo/README b/src/Modules/SimpleFifo/README new file mode 100644 index 0000000..6f1f65e --- /dev/null +++ b/src/Modules/SimpleFifo/README @@ -0,0 +1,11 @@ + Simple Fifo +-------------------- + + +Simple Fifo is a VHDL Module implementing a very simple Fifo with +configurable datawidth and depth... + +It uses a self written clock domain crossing component and a dual port block ram module. + +If you find bugs in these components, please fix them and send a pull request to +dmeyer@federationhq.de. \ No newline at end of file diff --git a/src/Modules/SimpleFifo/src/CDC_fifoIF.vhd b/src/Modules/SimpleFifo/src/CDC_fifoIF.vhd new file mode 100644 index 0000000..b824dc6 --- /dev/null +++ b/src/Modules/SimpleFifo/src/CDC_fifoIF.vhd @@ -0,0 +1,137 @@ +------------------------------------------------------- +--! @file +--! @brief Clock Domain Crossing Module +--! @author Dominik Meyer +--! @email dmeyer@federationhq.de +--! @date 2013-04-30 +------------------------------------------------------- + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + + +--! Clock Domain Crossing Module + +--! This component can be used to cross clock domain borders. +--! It is using a handshake protocol to make sure the data +--! has travelled across the border +entity CDC_fifoIF is + generic ( + GEN_Data_size : integer := 8 + ); + port ( + + idData : in std_logic_vector(GEN_Data_size-1 downto 0); --! data we want to send cross clock domains + icWe : in std_logic; --! data should be written to the other side + ocFull : out std_logic; --! module currently holds data + icWriteClk : in std_logic; --! write clock + + + odData : out std_logic_vector(GEN_Data_size-1 downto 0); --! data from the other side + ocDataAvail : out std_logic; --! data is available from module + icRe : in std_logic; --! ReadEnable signal + icReadClk : in std_logic; --! Read Clock + + icReset : in std_logic --! synchronous active high reset, triggered by the Write Clock, has to ne high at least 4 clock ticks + ); +end CDC_fifoIF; + +architecture arch of CDC_fifoIF is + + + signal srDataIn : std_logic_vector(GEN_Data_size-1 downto 0); + signal srDataOut : std_logic_vector(GEN_Data_size-1 downto 0); + signal scEnable : std_logic; + + signal scWEnableBuf : std_logic; + signal scWEnableBuf2 : std_logic; + signal scREnableBuf : std_logic; + signal scREnableBuf2 : std_logic; + signal scREnableBuf3 : std_logic; + signal scREnable : std_logic; + + signal scDataAvail : std_logic; + + + -- + -- Input FSM + -- + type INPUT_STATES is (s_start, s_idle, s_hold); + signal input_state : INPUT_STATES; + +begin + + ocFull <= scEnable or scREnableBuf3 or scREnableBuf2; + ocDataAvail <= (icRe or scDataAvail) and not scREnable; + + + input : process(icWriteClk) + begin + if (rising_edge(icWriteClk)) then + if (icReset = '1') then + + srDataIn <= (others => '0'); + scEnable <= '0'; + scREnableBuf <= '0'; + scREnableBuf2 <= '0'; + scREnableBuf3 <= '0'; + + else + + if (icWe = '1') then + srDataIn <= idData; + scEnable <= '1'; + elsif (scREnableBuf3 = '1') then + scEnable <= '0'; + else + scEnable <= scEnable; + end if; + + scREnableBuf <= scREnable; + scREnableBuf2 <= scREnableBuf; + scREnableBuf3 <= scREnableBuf2; + + end if; + end if; + end process; + + + + + output : process(icReadClk) + begin + if (rising_edge(icReadClk)) then + if (icReset = '1') then + scWEnableBuf <= '0'; + scWEnableBuf2 <= '0'; + scDataAvail <= '0'; + srDataOut <= (others => '0'); + scREnable <= '0'; + else + + if (icRe = '1') then + scREnable <= '1'; + elsif (scDataAvail = '0') then + scREnable <= '0'; + end if; + + if (scWEnableBuf2 = '1') then + srDataOut <= srDataIn; + else + srDataOut <= srDataOut; + end if; + + + scWEnableBuf <= scEnable; + scWEnableBuf2 <= scWEnableBuf; + scDataAvail <= scWEnableBuf2; + + end if; + end if; + end process; + + odData <= srDataOut; + +end arch; diff --git a/src/Modules/SimpleFifo/src/SimpleFifo.vhd b/src/Modules/SimpleFifo/src/SimpleFifo.vhd new file mode 100644 index 0000000..2512b70 --- /dev/null +++ b/src/Modules/SimpleFifo/src/SimpleFifo.vhd @@ -0,0 +1,325 @@ +------------------------------------------------------- +--! @file +--! @brief Simple Fifo, using the dual_port_block_ram to work on all FPGAs +--! @author Dominik Meyer +--! @email dmeyer@federationhq.de +--! @licence GPLv2 +--! @date 2013-11-20 +------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.std_logic_arith.all; + use ieee.math_real.all; + + +--! Simple Fifo, using the dual_port_block_ram to work on all FPGAs + +--! This is a very simple Fifo ! +entity SimpleFifo is + + generic ( + GEN_WIDTH : integer := 8; --! Data width of each data word + GEN_DEPTH : integer := 256; --! how many values can be stored in Fifo + + GEN_A_EMPTY : integer := 2; --! when is the FIFO signaled as almost empty + GEN_A_FULL : integer := 250 --! when is the FIFO signaled as almost full + + ); + + +port ( + odData : out std_logic_vector(GEN_WIDTH-1 downto 0); --! Data output of the fifo + icReadClk : in std_logic; --! read from fifo clock + icReadEnable : in std_logic; --! we have read the value + + + idData : in std_logic_vector(GEN_WIDTH-1 downto 0); --! data input to fifo + icWriteClk : in std_logic; --! clock for writing to the fifo + icWe : in std_logic; --! write enable for writing to the fifo + + ocEmpty : out std_logic; --! signal fifo empty + ocFull : out std_logic; --! signal fifo full + ocAempty : out std_logic; --! signal fifo almost empty + ocAfull : out std_logic; --! signal fifo almost full + + icClkEnable : in std_logic; --! active high clock enable signal + icReset : in std_logic --! active high reset, values in RAM are not overwritten, just FIFO + --! counters are resetted + +); + + +end SimpleFifo; + +architecture behavioral of SimpleFifo is + + component CDC_fifoIF + generic ( + GEN_Data_size : integer + ); + port ( + idData : in std_logic_vector ( GEN_Data_size - 1 downto 0 ); + icWe : in std_logic; + ocFull : out std_logic; + icWriteClk : in std_logic; + odData : out std_logic_vector ( GEN_Data_size - 1 downto 0 ); + ocDataAvail : out std_logic; + icRe : in std_logic; + icReadClk : in std_logic; + icReset : in std_logic + ); + end component; + + + component dual_port_block_ram + generic ( + GEN_WIDTH : integer; + GEN_DEPTH : integer; + GEN_ADDR_SIZE : integer + ); + port ( + icClkA : in std_logic; + icWeA : in std_logic; + icEnA : in std_logic; + idAddrA : in std_logic_vector ( GEN_ADDR_SIZE - 1 downto 0 ); + idDataA : in std_logic_vector ( GEN_WIDTH - 1 downto 0 ); + icClkB : in std_logic; + icEnB : in std_logic; + idAddrB : in std_logic_vector ( GEN_ADDR_SIZE - 1 downto 0 ); + odDataB : out std_logic_vector ( GEN_WIDTH - 1 downto 0 ) + ); + end component; + + + -- + -- General Signals + -- + signal scEmpty : std_logic; + signal scFull : std_logic; + + + -- + -- Signals for CDC + -- + signal sdRead2WriteIN : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH)))) downto 0); + signal sdRead2WriteOut : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH)))) downto 0); + signal scRead2WriteWe : std_logic; + signal scRead2WriteFull : std_logic; + signal scRead2WriteDA : std_logic; + signal scRead2WriteRe : std_logic; + + + signal sdWrite2ReadIN : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH)))) downto 0); + signal sdWrite2ReadOUT : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH)))) downto 0); + signal scWrite2ReadWe : std_logic; + signal scWrite2ReadFull : std_logic; + signal scWrite2ReadDA : std_logic; + signal scWrite2ReadRe : std_logic; + + -- + -- Signals for the Read side + -- + signal srReadAddr : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH))))-1 downto 0); + signal srReadOverflow : std_logic; + signal srWriteAddrRead : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH))))-1 downto 0); + signal srWriteOverflowRead : std_logic; + + signal srDataOut : std_logic_vector(GEN_WIDTH - 1 downto 0); + signal sdDataOut : std_logic_vector(GEN_WIDTH - 1 downto 0); + + -- + -- Signals for the Write side + -- + signal srWriteAddr : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH))))-1 downto 0); + signal srWriteOverflow : std_logic; + signal srReadAddrWrite : std_logic_vector(integer(ceil(log2(real(GEN_DEPTH))))-1 downto 0); + signal srReadOverflowWrite : std_logic; + + + -- signals for RAM + signal scRAMwriteEnable : std_logic; + + +begin + + ocEmpty <= scEmpty; + ocFull <= scFull; + + + scRAMwriteEnable <= not scFull and icWe; + + ram0 : dual_port_block_ram + generic map( + GEN_WIDTH => GEN_WIDTH, + GEN_DEPTH => GEN_DEPTH, + GEN_ADDR_SIZE => integer(ceil(log2(real(GEN_DEPTH)))) + ) + port map( + icClkA => icWriteClk, + icWeA => scRAMwriteEnable, + icEnA => icClkEnable, + idAddrA => srWriteAddr, + idDataA => idData, + icClkB => icWriteClk, + icEnB => icClkEnable, + idAddrB => srReadAddr, + odDataB => odData + ); + + scFull <= '1' when srWriteOverflow = '0' and srReadOverflowWrite = '0' and srWriteAddr - srReadAddrWrite >= GEN_DEPTH-1 else + '1' when srWriteOverflow = '1' and srReadOverflowWrite = '0' and GEN_DEPTH-srReadAddrWrite+srWriteAddr >= GEN_DEPTH-1 else + '1' when srWriteOverflow = '0' and srReadOverflowWrite = '1' and GEN_DEPTH-srReadAddrWrite+srWriteAddr >= GEN_DEPTH-1 else + '1' when srWriteOverflow = '1' and srWriteOverflowRead = '1' and srWriteAddr - srReadAddrWrite >= GEN_DEPTH-1 else + '0'; + + scEmpty <= '1' when srWriteOverflowRead = '0' and srReadOverflow = '0' and srWriteAddrRead - srReadAddr = 0 else + '1' when srWriteOverflowRead = '1' and srReadOverflow = '1' and srWriteAddrRead - srReadAddr = 0 else + '0'; + + + + ocAfull <= '1' when srWriteOverflow = '0' and srReadOverflowWrite = '0' and srWriteAddr - srReadAddrWrite >= GEN_A_FULL else + '1' when srWriteOverflow = '1' and srReadOverflowWrite = '0' and GEN_DEPTH-srReadAddrWrite+srWriteAddr >= GEN_A_FULL else + '1' when srWriteOverflow = '0' and srReadOverflowWrite = '1' and GEN_DEPTH-srReadAddrWrite+srWriteAddr >= GEN_A_FULL else + '1' when srWriteOverflow = '1' and srWriteOverflowRead = '1' and srWriteAddr - srReadAddrWrite >= GEN_A_FULL else + '0'; + + + ocAempty <= '1' when srWriteOverflow = '0' and srReadOverflowWrite = '0' and srWriteAddr - srReadAddrWrite <= GEN_A_EMPTY else + '1' when srWriteOverflow = '1' and srReadOverflowWrite = '0' and GEN_DEPTH-srReadAddrWrite+srWriteAddr <= GEN_A_EMPTY else + '1' when srWriteOverflow = '0' and srReadOverflowWrite = '1' and GEN_DEPTH-srReadAddrWrite+srWriteAddr <= GEN_A_EMPTY else + '1' when srWriteOverflow = '1' and srWriteOverflowRead = '1' and srWriteAddr - srReadAddrWrite <= GEN_A_EMPTY else + '0'; + + + -- write FSM + Writefsm : process(icWriteClk) + begin + if (rising_edge(icWriteClk)) then + if (icReset = '1') then + + srWriteAddr <= (others => '0'); + srWriteOverflow <= '0'; + + srReadAddrWrite <= (others => '0'); + srReadOverflowWrite <= '0'; + + elsif (icClkEnable = '1') then + + if (scWrite2ReadFull = '0') then + scWrite2ReadWe <= '1'; + else + scWrite2ReadWe <= '0'; + end if; + + if (scRead2WriteDA = '1') then + scRead2WriteRe <= '1'; + srReadAddrWrite <= sdRead2WriteOUT(integer(ceil(log2(real(GEN_DEPTH)))) downto 1); + srReadOverflowWrite <= sdRead2WriteOUT(0); + else + scRead2WriteRe <= '0'; + end if; + + if (icWe = '1' and scFull = '0') then + if (srWriteAddr >= GEN_DEPTH-1 ) then + srWriteAddr <= (others => '0'); + srWriteOverflow <= not srWriteOverflow; + else + srWriteAddr <= srWriteAddr + 1; + end if; + end if; + + end if; + end if; + end process; + + + cdcWrite2Read : CDC_fifoIF + generic map( + GEN_Data_size => integer(ceil(log2(real(GEN_DEPTH))))+1 + ) + port map( + idData => sdWrite2ReadIN, + icWe => scWrite2ReadWe, + ocFull => scWrite2ReadFull, + icWriteClk => icWriteClk, + odData => sdWrite2ReadOUT, + ocDataAvail => scWrite2ReadDA, + icRe => scWrite2ReadRe, + icReadClk => icReadClk, + icReset => icReset + ); + + + sdWrite2ReadIN <= srWriteAddr & srWriteOverflow; + + + + + + -- write FSM + Readfsm : process(icReadClk) + begin + if (rising_edge(icReadClk)) then + if (icReset = '1') then + + srReadAddr <= (others => '0'); + srWriteAddrRead <= (others => '0'); + srWriteOverflowRead <= '0'; + srReadOverflow <= '0'; + + elsif (icClkEnable = '1') then + + if (scRead2WriteFull = '0') then + scRead2WriteWe <= '1'; + else + scRead2WriteWe <= '0'; + end if; + + if (scWrite2ReadDA = '1') then + scWrite2ReadRe <= '1'; + srWriteAddrRead <= sdWrite2ReadOUT(integer(ceil(log2(real(GEN_DEPTH)))) downto 1); + srWriteOverflowRead <= sdWrite2ReadOut(0); + else + scWrite2ReadRe <= '0'; + end if; + + if (icReadEnable = '1' and scEmpty = '0') then + if (srReadAddr >= GEN_DEPTH-1) then + srReadAddr <= (others => '0'); + srReadOverflow <= not srReadOverflow; + else + srReadAddr <= srReadAddr + 1; + end if; + end if; + + end if; + end if; + end process; + + + cdcRead2Write : CDC_fifoIF + generic map( + GEN_Data_size => integer(ceil(log2(real(GEN_DEPTH))))+1 + ) + port map( + idData => sdRead2WriteIN, + icWe => scRead2WriteRe, + ocFull => scRead2WriteFull, + icWriteClk => icWriteClk, + odData => sdRead2WriteOut, + ocDataAvail => scRead2WriteDA, + icRe => scRead2WriteRe, + icReadClk => icReadClk, + icReset => icReset + ); + + + + sdRead2WriteIN <= srReadAddr & srReadOverflow; + + + +end behavioral; diff --git a/src/Modules/SimpleFifo/src/dual_port_block_ram.vhd b/src/Modules/SimpleFifo/src/dual_port_block_ram.vhd new file mode 100644 index 0000000..8601167 --- /dev/null +++ b/src/Modules/SimpleFifo/src/dual_port_block_ram.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------- +--! @file +--! @brief dual port block ram description - write to one port, read from the other +--! @author Dominik Meyer +--! @email dmeyer@federationhq.de +--! @licence GPLv2 +--! @date 2013-11-20 +------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.std_logic_arith.all; + + +--! dual port block ram description - write to one port, read from the other + +--! dual port block ream description +--! Port A is used for writing to the ram, while Port B is used for reading only. +--! written in a way that the Xilinx Tools will use the onboard block ram +--! if available, otherwise using logic cells +entity dual_port_block_ram is + + generic ( + GEN_WIDTH : integer := 8; --! the width of one data word + GEN_DEPTH : integer := 256; --! how many words should be storeable in the ram + GEN_ADDR_SIZE : integer := 8 --! how many address bits shall be used + + ); + + + port ( + icClkA : in std_logic; --! clock for port A + icWeA : in std_logic; --! active high write enable for port A + icEnA : in std_logic; --! active high enable for port A + idAddrA : in std_logic_vector(GEN_ADDR_SIZE - 1 downto 0); --! address for port A + idDataA : in std_logic_vector(GEN_WIDTH - 1 downto 0); --! data input for port A + + icClkB : in std_logic; --! clock for port B + icEnB : in std_logic; --! active high enable signal for port B + idAddrB : in std_logic_vector(GEN_ADDR_SIZE - 1 downto 0); --! address for port B + odDataB : out std_logic_vector(GEN_WIDTH - 1 downto 0) --! data output of port B + + ); + +end dual_port_block_ram; + +architecture behavioral of dual_port_block_ram is + + type ramType is array (0 to GEN_DEPTH-1) of std_logic_vector(GEN_WIDTH-1 downto 0); + signal ram : ramType := (others => (others => '0')); + + signal sdDataOut : std_logic_vector(GEN_WIDTH-1 downto 0); + +begin + + portA : process(icClkA) + begin + if (rising_edge(icClkA)) then + if (icEnA = '1') then + if (icWeA = '1') then + ram(conv_integer(idAddrA)) <= idDataA; + end if; + end if; + end if; + end process; + + + + portB : process(icClkB) + begin + if (rising_edge(icClkB)) then + if (icEnB = '1') then + sdDataOut <= ram(conv_integer(idAddrB)); + end if; + end if; + + end process; + + odDataB <= sdDataOut; + +end behavioral;