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FIX: fixed file headers, added licence, formated code

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Dominik Meyer 2013-12-30 14:56:42 +01:00
parent 2ff599262a
commit aa3ed4c103
5 changed files with 727 additions and 740 deletions
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82
src/ALU.vhd
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@ -1,60 +1,59 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:27 05/10/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Simple ALU for the Simple Processor Core (Geraffel Processor)
--! @author Dominik Meyer/ Marcel Eckert
--! @email dmeyer@federationhq.de
--! @licence GPLv2
--! @date unknown
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use work.cpupkg.all;
--! A very Simple ALU to support all the arithmetical and logical operation of the
--! Simple Processor Core (Geraffel Processor Core)
--!
--! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
--!
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port(
idOperand1 : in DATA;
idOperand2 : in DATA;
idCarryIn : in std_logic;
idImmidiate : in DATA;
odResult : out DATA;
odCarryOut : out std_logic;
odZeroOut : out std_logic;
icOperation : in OPTYPE
port(
idOperand1 : in DATA; --! first Operand for any operation
idOperand2 : in DATA; --! second Operand for any operation
idCarryIn : in std_logic; --! Carry Input for any arithmetical operation
idImmidiate : in DATA; --! Immediate input for operation requiring an immediat
odResult : out DATA; --! Result output of any operation
odCarryOut : out std_logic; --! Output of the Carry, if generated by an operation
odZeroOut : out std_logic; --! is the result zero flag output
icOperation : in OPTYPE --! which Operation to perform
);
end ALU;
--! Architectural description of the ALU
architecture Behavioral of ALU is
signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(32 downto 0);
begin
-- extend the operand by one bit, to be able to get the overflow
-- of an operation
sdOp1 <= '0' & idOperand1;
sdOp2 <= '0' & idOperand2;
--! process to do the actual computation
process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate, idOperand1)
begin
-- TODO: convert to case structure for improved space usege and speed
if (icOperation = shl) then
sdTempResult <= sdOp1(31 downto 0) & "0";
@ -107,10 +106,11 @@ begin
end if;
end process;
-- output the generated signals
odResult <= sdTempResult(31 downto 0);
odCarryOut <= sdTempResult(32);
odZeroOut <= '1' when sdTempResult(31 downto 0) = 0 else
'0';
end Behavioral;

95
src/ControlUnit.vhd
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@ -1,20 +1,26 @@
-------------------------------------------------------
--! @file
--! @brief the control unit of the IIB2 Akkumulator machine
--! @brief the control unit for the Simple Processor Core (Geraffel Processor)
--! @author Dominik Meyer
--! @email dmeyer@hsu-hh.de
--! @licence GPLv2
--! @date 2010-11-19
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.cpupkg.all;
use work.cpupkg.all;
entity Steuerwerk is
--! the control unit for the Simple Processor Core (Geraffel Processor)
--!
--! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
--!
entity ControlUnit is
port (
iClk : in std_logic; --! iClk signal
iReset : in std_logic; --! iReset signal
@ -32,31 +38,34 @@ entity Steuerwerk is
ocUsePC : out std_logic; --! use Register to fill in the PC
ocLoad : out std_logic --! put databus to ALU immediate port
);
end Steuerwerk;
end ControlUnit;
architecture arch of Steuerwerk is
architecture arch of ControlUnit is
type STATES is (load, decode, exshl, exshr, exsto, exloa, exli, exadd, exsub, exaddc, exsubc,
type STATES is (load, decode, exshl, exshr, exsto, exloa, exloa2, exli, exadd, exsub, exaddc, exsubc,
exopor, exopand, exopxor, exopnot, exjpz, exjpc, exjmp, exhlt, exjmc, exret);
signal sState, sState_next : STATES;
signal sState, sState_next : STATES;
begin
-- switch sStates if needed
sState_change: process(iClk,iReset)
begin
--! switch sStates if needed
sState_change : process(iClk,iReset)
begin
if (iReset = '1') then
sState <= load;
elsif (rising_edge(iClk)) then
sState <= sState_next;
end if;
end process;
end process;
calc_sState_next: process(sState, icOpCode, idCarry, idZero)
begin
--! calculate the next state of the FSM
calc_sState_next : process(sState, icOpCode, idCarry, idZero)
begin
case sState is
when load =>
@ -76,12 +85,14 @@ begin
when opor => sState_next <= exopor;
when opxor => sState_next <= exopxor;
when opnot => sState_next <= exopnot;
when jpz => if (idZero = '1') then
when jpz =>
if (idZero = '1') then
sState_next <= exjpz;
else
sState_next <= load;
end if;
when jpc => if (idCarry = '1') then
when jpc =>
if (idCarry = '1') then
sState_next <= exjpc;
else
sState_next <= load;
@ -92,16 +103,17 @@ begin
when hlt => sState_next <= exhlt;
end case;
when exhlt => sState_next <= exhlt;
when exloa => sState_next <= exloa2;
when others => sState_next <= load;
end case;
end process;
end process;
--! calculate the output in each sState
calc_output: process(sState)
begin
calc_output : process(sState)
begin
case sState is
@ -175,7 +187,8 @@ begin
ocJump <= '0'; -- no ocJump
ocPCregister <= '0'; -- do not put PC to register File
ocUsePC <= '0';
ocLoad <= '1';
ocLoad <= '0';
when exli =>
ocRnotWRam <= '0'; -- read from RAM
@ -224,6 +237,17 @@ begin
ocPCregister <= '0'; -- do not put PC to register File
ocUsePC <= '0';
ocLoad <= '0';
when exloa2 =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
ocPCregister <= '0'; -- do not put PC to register File
ocUsePC <= '0';
ocLoad <= '1';
when exsubc =>
ocRnotWRam <= '0'; -- read from RAM
@ -329,7 +353,7 @@ begin
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '1'; -- ocJump
ocPCregister<= '1'; -- put PC to register File
ocPCregister <= '1'; -- put PC to register File
ocUsePC <= '0';
ocLoad <= '0';
@ -341,7 +365,7 @@ begin
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- ocJump
ocPCregister<= '0'; -- put PC to register File
ocPCregister <= '0'; -- put PC to register File
ocUsePC <= '1';
ocLoad <= '0';
@ -371,26 +395,7 @@ begin
end case;
end process;
end process;
end arch;

110
src/FetchDecode.vhd
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@ -1,57 +1,44 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:16:43 05/10/2011
-- Design Name:
-- Module Name: FetchDecode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Fetch/Decode Component for the Simple Processor Core (Geraffel Processor)
--! @author Dominik Meyer/ Marcel Eckert
--! @email dmeyer@federationhq.de
--! @licence GPLv2
--! @date unknown
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.cpupkg.all;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! Fetch/Decode Component for the Simple Processor Core (Geraffel Processor)
--!
--! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
--!
entity FetchDecode is
Port(
iClk : in std_logic;
iReset : in std_logic;
port(
idData : in DATA;
icAddrSel : in std_logic;
icLoadInstr : in std_logic;
icJump : in std_logic;
icNextPC : in std_logic;
odPC : out ADDRESS;
idPC : in ADDRESS;
icUsePC : in std_logic;
odAddress : out ADDRESS;
odImmidiate : out DATA;
odRegAsel : out std_logic_vector(4 downto 0);
odRegBsel : out std_logic_vector(4 downto 0);
odRegINsel : out std_logic_vector(4 downto 0);
ocOperation : out OPTYPE
iClk : in std_logic; --! main system clock
iReset : in std_logic; --! system active high reset
idData : in DATA; --! Data input coming from the RAM with instruction
icAddrSel : in std_logic; --! Put AddressRegister to Address BUS
icDecodeInstr : in std_logic; --! Decode the loaded instrcution
icJump : in std_logic; --! executed instruction is a jump, put jump register to address bus
icNextPC : in std_logic; --! increment the PC
odPC : out ADDRESS; --! put out the current PC
idPC : in ADDRESS; --! input for a new PC from extern
icUsePC : in std_logic; --! use the external PC
odAddress : out ADDRESS; --! output to the address bus
odImmidiate : out DATA; --! output the loaded immediate
odRegAsel : out std_logic_vector(4 downto 0); --! output the decoded register addr
odRegBsel : out std_logic_vector(4 downto 0); --! output the decoded register addr
odRegINsel : out std_logic_vector(4 downto 0); --! output the decoded result register addr
ocOperation : out OPTYPE --! output which operation to perform
);
end FetchDecode;
@ -68,26 +55,33 @@ architecture Behavioral of FetchDecode is
signal scOp, scOp_next : OPTYPE;
begin
Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp, sdRegAsel, sdRegBsel, sdRegINsel, icUsePC, idPC)
Transition : process(idData, sdImmidate, icDecodeInstr, icJump, icNextPC, sdAdr, sdPC, scOp, sdRegAsel, sdRegBsel, sdRegINsel, icUsePC, idPC)
begin
-- defaults
-- default values for all signals/registers
sdAdr_next <= sdAdr;
sdPC_next <= sdPC;
scOp_next <= scOp;
sdImmidiate_next <= sdImmidate;
-- fill the next register values with the old ones
sdRegAsel_next <= sdRegAsel;
sdRegBsel_next <= sdRegBsel;
sdRegINsel_next <= sdRegINsel;
--! ISA Definition
if (icLoadInstr = '1') then
--! ISA Definition, for the Decode run
if (icDecodeInstr = '1') then
-- because of the fixed bit positions we can fill in the correct values to the next register values
sdAdr_next <= idData(15 downto 0);
sdImmidiate_next <= "0000000000000000" & idData(15 downto 0);
sdRegINsel_next <= idData(25 downto 21);
sdRegAsel_next <= idData(20 downto 16);
sdRegBsel_next <= idData(15 downto 11);
-- select the operation to do according to the decoded opcode
case idData(31 downto 26) is
when "000000" => scOp_next <= shl;
when "000001" => scOp_next <= shr;
@ -111,6 +105,7 @@ begin
end case;
end if;
-- set registers according of some special external control signals
if (icUsePC = '1') then
sdPC_next <= idPC;
end if;
@ -128,16 +123,16 @@ begin
end process;
-- Execute Transition
-- Execute Transition, set register values to the calculated next register values
process(iClk, iReset)
begin
if (iReset = '1') then
sdPC <= (others => '0');
sdAdr <= (others => '0');
sdImmidate <= (others=>'0');
sdRegAsel <= (others=>'0');
sdRegBsel <= (others=>'0');
sdRegINsel <= (others=>'0');
sdImmidate <= (others => '0');
sdRegAsel <= (others => '0');
sdRegBsel <= (others => '0');
sdRegINsel <= (others => '0');
scOp <= hlt;
@ -153,7 +148,7 @@ begin
end process;
-- Output
-- Output everything to the correct output signal
odAddress <= idPC when icUsePC = '1' else
sdAdr when icAddrSel = '0' and icLoadInstr = '0' else
sdAdr_next when icAddrSel = '0' and icLoadInstr = '1' else
@ -172,4 +167,3 @@ begin
end Behavioral;

11
src/MemoryMapper.vhd
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@ -2,14 +2,12 @@
--! @file
--! @brief Maps memory devices to a given memory space
--! @author Dominik Meyer
--! @email dmeyer@hsu-hh.de
--! @email dmeyer@federationhq.de
--! @date 2010-06-03
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--! Maps memory devices to a given memory space
@ -17,9 +15,7 @@ entity MemoryMapper is
port(
start : in std_logic_vector(15 downto 0); --! start of memory space
stop : in std_logic_vector(15 downto 0); --! end of mempry space
adr_in : in std_logic_vector(15 downto 0);
req_in : in std_logic; --! ram request type
req_out : out std_logic; --! ram request type
@ -51,4 +47,3 @@ begin
end process;
end arch;

73
src/RegFile.vhd
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@ -1,53 +1,47 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:19 05/10/2011
-- Design Name:
-- Module Name: RegFile - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief RegisterFile for the Simple Processor Core (Geraffel Processor)
--! @author Dominik Meyer
--! @email dmeyer@federationhq.de
--! @licence GPLv2
--! @date unknown
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.cpupkg.all;
use ieee.numeric_std.all;
use work.cpupkg.all;
use ieee.numeric_std.all;
--! RegisterFile for the Simple Processor Core (Geraffel Processor)
--!
--! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
--!
entity RegFile is
Port(
iClk : in std_logic;
iReset : in std_logic;
port(
iClk : in std_logic; --! main sytem clock signal
iReset : in std_logic; --! main system active high reset
icRegAsel : in std_logic_vector(4 downto 0);
icRegBsel : in std_logic_vector(4 downto 0);
odRegA : out DATA;
odRegB : out DATA;
icRegAsel : in std_logic_vector(4 downto 0); --! address of register A
icRegBsel : in std_logic_vector(4 downto 0); --! address of register B
odRegA : out DATA; --! output of the register A Value
odRegB : out DATA; --! output of the register B Value
icPC : in std_logic; -- select PC as input to RegisterFile
idPC : in DATA;
icPC : in std_logic; --! select the PC Input as the input value, required for ret instruction
idPC : in DATA; --! input of the PC, required for the ret instruction
icRegINsel : in std_logic_vector(4 downto 0);
icRegINsel : in std_logic_vector(4 downto 0); --! address of the register to which to save the input
idDataIn : in DATA;
idCarryIn : in std_logic;
idZeroIn : in std_logic;
idDataIn : in DATA; --! data input, normally from the ALU
idCarryIn : in std_logic; --! Carry Flag of the last Operation
idZeroIn : in std_logic; --! Zero Flag of the last Operation
icLoadEn : in std_logic;
icLoadEn : in std_logic; --! actually save the input Data to the selected register
odCarryOut : out std_logic;
odZeroOut : out std_logic
odCarryOut : out std_logic; --! output of the currently saved carry flag
odZeroOut : out std_logic --! output of the currently saved zero flag
);
end RegFile;
@ -70,7 +64,7 @@ begin
begin
if (iReset = '1') then
for i in 31 downto 0 loop
registerFile(i) <= (others=>'0');
registerFile(i) <= (others => '0');
end loop;
sdCarry <= '0';
@ -99,4 +93,3 @@ begin
odZeroOut <= sdZero;
end Behavioral;