FIX: fixes and ADD: small assembler
This commit is contained in:
parent
bc07966401
commit
a53abe0ff9
12
asm/mult.s
Normal file
12
asm/mult.s
Normal file
@ -0,0 +1,12 @@
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lui $1, 5
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lui $2, 6
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lui $3, 0
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lui $4, 1
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add $5, $0, $2
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loop:
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add $3, $3, $1
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sub $5, $5, $4
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jpz end
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jmp loop
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end:
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hlt
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375
scripts/asm.pl
Executable file
375
scripts/asm.pl
Executable file
@ -0,0 +1,375 @@
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#!/usr/bin/perl
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#
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# Small assembler for the Simple Processor Core
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#
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my $nr_instr_bytes = 4;
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my $nr_opcode_bits = 6;
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my $nr_reg_bits = 5;
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my $startaddr = 0;
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# mnemonnic to opcode conversion
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my %opcodes = (
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'shl' => 0x00,
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'shr' => 0x01,
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'sto' => 0x02,
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'loa' => 0x03,
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'add' => 0x04,
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'sub' => 0x05,
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'addc' => 0x06,
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'subc' => 0x07,
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'or' => 0x08,
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'and' => 0x09,
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'xor' => 0x0A,
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'not' => 0x0B,
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'jpz' => 0x0C,
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'jpc' => 0x0D,
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'jmp' => 0x0E,
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'lui' => 0x0F,
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'hlt' => 0x3F
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);
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#---------------------------------------------------------------------------
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# main program
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#---------------------------------------------------------------------------
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my $filename = $ARGV[0];
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my %labels;
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# check if file exists
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if ( !-e $filename ) {
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die("file does not exist\n");
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}
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open my $src, "<" . $filename;
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my $addr = $startaddr;
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my $lines = 0;
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my @instructions;
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my $valid;
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while ( my $line = <$src> ) {
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$line =~ /^(\S+)\s(.*)$/;
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my $INSTR = $1;
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my $REST = $2;
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$addr++;
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$lines++;
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my $opc = $opcodes{"$INSTR"};
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my $label = "";
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$opc = $opc << 26;
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$valid = 1;
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if ( $INSTR eq "shl" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for shl in line $lines\n");
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}
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}
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elsif ( $INSTR eq "shr" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for shr in line $lines\n");
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}
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}
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elsif ( $INSTR eq "sto" ) {
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if ( $REST =~ /^\$(.*),(.*)$/ ) {
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my $dst = $1;
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$dst =~ s/\s//g;
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$dst = $dst << 16;
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$opc = $opc | $dst;
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my $imm = $2;
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$imm =~ s/\s//g;
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$opc = $opc | $imm;
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}
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else {
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die("ASM: wrong number of parameters for sto in line $lines\n")
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;
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}
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}
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elsif ( $INSTR eq "loa" ) {
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if ( $REST =~ /^\$(.*),(.*)$/ ) {
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my $dst = $1;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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my $imm = $2;
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$imm =~ s/\s//g;
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$opc = $opc | $imm;
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}
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else {
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die("ASM: wrong number of parameters for sto in line $lines\n")
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;
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}
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}
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elsif ( $INSTR eq "add" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for add in line $lines\n");
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}
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}
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elsif ( $INSTR eq "sub" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for sub in line $lines\n");
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}
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}
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elsif ( $INSTR eq "addc" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for addc in line $lines\n");
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}
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}
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elsif ( $INSTR eq "subc" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for subc in line $lines\n");
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}
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}
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elsif ( $INSTR eq "or" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for or in line $lines\n");
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}
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}
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elsif ( $INSTR eq "and" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for and in line $lines\n");
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}
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}
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elsif ( $INSTR eq "xor" ) {
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if ( $REST =~ /^[\s\$]+(.*),[\s\$]+(.*),[\s\$]+(.*)$/ ) {
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my $dst = $1;
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my $op1 = $2;
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my $op2 = $3;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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$op1 =~ s/\s//g;
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$op1 = $op1 << 16;
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$opc = $opc | $op1;
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$op2 =~ s/\s//g;
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$op2 = $op2 << 11;
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$opc = $opc | $op2;
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}
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else {
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die("ASM: wrong number of parameters for xor in line $lines\n");
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}
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}
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elsif ( $INSTR eq "not" ) {
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if ( $REST =~ /^[\s\$]+(.*)$/ ) {
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my $dst = $1;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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}
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else {
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die("ASM: wrong number of parameters for add in line $lines\n");
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}
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}
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elsif ( $INSTR eq "jpz" ) {
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$label = $REST;
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}
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elsif ( $INSTR eq "jpc" ) {
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$label = $REST;
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}
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elsif ( $INSTR eq "jmp" ) {
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$label = $REST;
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}
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elsif ( $INSTR eq "hlt" ) {
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}
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elsif ( $INSTR eq "lui" ) {
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if ( $REST =~ /^\$(.*),(.*)$/ ) {
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my $dst = $1;
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$dst =~ s/\s//g;
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$dst = $dst << 21;
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$opc = $opc | $dst;
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my $imm = $2;
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$imm =~ s/\s//g;
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$opc = $opc | $imm;
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}
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else {
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die("ASM: wrong number of parameters for lui in line $lines\n")
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;
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}
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}
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elsif ( $INSTR =~ /^(.*):$/ ) {
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$labels{$1} = $addr;
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$addr--;
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$valid = 0;
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}
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else {
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$addr--;
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$valid = 0;
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}
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if ( $valid == 1 ) {
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$line =~ s/\n//;
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my $instruction = {};
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$instruction->{addr} = $addr;
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$instruction->{opc} = $opc;
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$instruction->{comment} = $line;
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$instruction->{label} = $label;
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push( @instructions, $instruction );
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}
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}
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close $src;
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# correct labels
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for my $i (@instructions) {
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if ( $i->{label} =~ /\S+/ ) {
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for my $l ( keys %labels ) {
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if ( $i->{label} eq $l ) {
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$i->{opc} = $i->{opc} | $labels{$l};
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}
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}
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}
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}
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for my $i (@instructions) {
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if ($ARGV[1] eq "-vhdl") {
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printf("%4s \t => B\"%.32b\", --%s\n ",$i->{addr}, $i->{opc}, $i->{comment});
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} else {
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printf( "%4s %.32b #%s\n", $i->{addr}, $i->{opc}, $i->{comment} );
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}
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}
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33
src/CPU.vhd
33
src/CPU.vhd
@ -66,13 +66,20 @@ architecture Behavioral of CPU is
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iClk : in std_logic;
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iReset : in std_logic;
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icRegAsel : in std_logic_vector(4 downto 0);
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icRegBsel : in std_logic_vector(4 downto 0);
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odRegA : out DATA;
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odRegB : out DATA;
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icRegINsel : in std_logic_vector(4 downto 0);
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idDataIn : in DATA;
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idCarryIn : in std_logic;
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idZeroIn : in std_logic;
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icLoadEn : in std_logic;
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odDataOut : out DATA;
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odCarryOut : out std_logic;
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odZeroOut : out std_logic
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);
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@ -106,6 +113,9 @@ architecture Behavioral of CPU is
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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odRegAsel : out std_logic_vector(4 downto 0);
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odRegBsel : out std_logic_vector(4 downto 0);
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odRegINsel : out std_logic_vector(4 downto 0);
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ocOperation : out OPTYPE
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);
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end component;
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@ -142,6 +152,11 @@ architecture Behavioral of CPU is
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signal sdDataIn : DATA;
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signal sdAddress : ADDRESS;
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signal sdImmidiate : DATA;
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signal sdRegAsel : std_logic_vector(4 downto 0);
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signal sdRegBsel : std_logic_vector(4 downto 0);
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signal sdRegINsel : std_logic_vector(4 downto 0);
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signal sdRegA : DATA;
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signal sdRegB : DATA;
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begin
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@ -164,20 +179,25 @@ begin
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iClk => iClk,
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iReset => iReset,
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icRegAsel => sdRegAsel,
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icRegBsel => sdRegBsel,
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icRegINsel => sdRegINsel,
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idDataIn => sdAkkuRes,
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idCarryIn => sdCarryAkku,
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idZeroIn => sdZeroAkku,
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icLoadEn => scLoadEn,
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odDataOut => sdDataOut,
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odRegA => sdRegA,
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odRegB => sdRegB,
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odCarryOut => sdCarryRF,
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odZeroOut => sdZeroRF
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);
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Calc : ALU Port MAP(
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idOperand1 => sdDataOut,
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idOperand2 => sdDataIn,
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idOperand1 => sdRegA,
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idOperand2 => sdRegB,
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idImmidiate => sdImmidiate,
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idCarryIn => sdCarryRF,
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@ -200,6 +220,9 @@ begin
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odAddress => sdAddress,
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odImmidiate => sdImmidiate,
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odRegAsel => sdRegAsel,
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odRegBsel => sdRegBsel,
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odRegINsel => sdRegINsel,
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ocOperation => scOpCode
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);
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@ -212,7 +235,7 @@ begin
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icBusCtrlCPU => scRnotWRam,
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icRAMEnable => scEnableRAM,
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odDataOutCPU => sdDataIn,
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idDataInCPU => sdDataOut,
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idDataInCPU => sdRegA,
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idAddressCPU => sdAddress
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);
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@ -46,7 +46,11 @@ entity FetchDecode is
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odAddress : out ADDRESS;
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odImmidiate : out DATA;
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odRegAsel : out std_logic_vector(4 downto 0);
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odRegBsel : out std_logic_vector(4 downto 0);
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odRegINsel : out std_logic_vector(4 downto 0);
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ocOperation : out OPTYPE
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);
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end FetchDecode;
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@ -55,10 +59,14 @@ architecture Behavioral of FetchDecode is
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signal sdAdr, sdAdr_next : ADDRESS;
|
||||
signal sdImmidate, sdImmidiate_next : DATA;
|
||||
|
||||
signal sdRegAsel, sdRegAsel_next : std_logic_vector(4 downto 0);
|
||||
signal sdRegBsel, sdRegBsel_next : std_logic_vector(4 downto 0);
|
||||
signal sdRegINsel, sdRegINsel_next : std_logic_vector(4 downto 0);
|
||||
|
||||
signal scOp, scOp_next : OPTYPE;
|
||||
|
||||
begin
|
||||
Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp)
|
||||
Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp, sdRegAsel, sdRegBsel, sdRegINsel)
|
||||
begin
|
||||
-- defaults
|
||||
sdAdr_next <= sdAdr;
|
||||
@ -66,10 +74,17 @@ begin
|
||||
scOp_next <= scOp;
|
||||
sdImmidiate_next <= sdImmidate;
|
||||
|
||||
sdRegAsel_next <= sdRegAsel;
|
||||
sdRegBsel_next <= sdRegBsel;
|
||||
sdRegINsel_next <= sdRegINsel;
|
||||
|
||||
--! ISA Definition
|
||||
if (icLoadInstr = '1') then
|
||||
sdAdr_next <= idData(15 downto 0);
|
||||
sdAdr_next <= "0000" & idData(11 downto 0);
|
||||
sdImmidiate_next <= "0000000000000000" & idData(15 downto 0);
|
||||
sdRegINsel_next <= idData(25 downto 21);
|
||||
sdRegAsel_next <= idData(20 downto 16);
|
||||
sdRegBsel_next <= idData(15 downto 11);
|
||||
|
||||
case idData(31 downto 26) is
|
||||
when "000000" => scOp_next <= shl;
|
||||
@ -111,6 +126,10 @@ begin
|
||||
sdPC <= (others => '0');
|
||||
sdAdr <= (others => '0');
|
||||
sdImmidate <= (others=>'0');
|
||||
sdRegAsel <= (others=>'0');
|
||||
sdRegBsel <= (others=>'0');
|
||||
sdRegINsel <= (others=>'0');
|
||||
|
||||
scOp <= hlt;
|
||||
|
||||
elsif (rising_edge(iClk)) then
|
||||
@ -118,6 +137,9 @@ begin
|
||||
sdAdr <= sdAdr_next;
|
||||
scOp <= scOp_next;
|
||||
sdImmidate <= sdImmidiate_next;
|
||||
sdRegAsel <= sdRegAsel_next;
|
||||
sdRegBsel <= sdRegBsel_next;
|
||||
sdRegINsel <= sdRegINsel_next;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
@ -131,5 +153,11 @@ begin
|
||||
scOp_next;
|
||||
|
||||
odImmidiate <= sdImmidate when icLoadInstr = '0' else sdImmidiate_next;
|
||||
|
||||
odRegAsel <= sdRegAsel when icLoadInstr = '0' else sdRegAsel_next;
|
||||
odRegBsel <= sdRegBsel when icLoadInstr = '0' else sdRegBsel_next;
|
||||
odRegINsel <= sdRegINsel when icLoadInstr = '0' else sdRegINsel_next;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@ architecture Behavioral of MemInterface is
|
||||
begin
|
||||
|
||||
ocRnotW <= icBusCtrlCPU;
|
||||
odAddress <= idAddressCPU;
|
||||
odAddress <= idAddressCPU when icRAMEnable='1' else (others=>'0');
|
||||
ocEnable <= icRAMEnable;
|
||||
|
||||
odDataOutCPU <= bdDataBus;
|
||||
|
||||
27
src/RAM.vhd
27
src/RAM.vhd
@ -34,22 +34,17 @@ architecture arch of RAM is
|
||||
type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
|
||||
|
||||
constant Prog1 : MEMORY := ( --! 4k * 32bit of RAM
|
||||
0 => B"001111_000_000_000_0_0000000000000101", -- li 5
|
||||
1 => B"000010_000_000_000_0_0000000000100000", -- sto 32
|
||||
2 => B"111111_000_000_000_0_0000000000000000", -- hlt
|
||||
-- 0 => B"0011_000000001010", -- loa 10 (n)
|
||||
-- 1 => B"1100_000000001000", -- jpz 8
|
||||
-- 2 => B"0101_000000001100", -- sub <1>
|
||||
-- 3 => B"0010_000000001010", -- sto 10 (n)
|
||||
-- 4 => B"0011_000000001011", -- loa 11 (a)
|
||||
-- 5 => B"0100_000000001001", -- add <result>
|
||||
-- 6 => B"0010_000000001001", -- sto <result>
|
||||
-- 7 => B"1110_000000000000", -- jmp 0
|
||||
-- 8 => B"1111_000000000000", -- hlt
|
||||
-- 9 => B"0000_000000000000", -- result
|
||||
-- 10 => B"0000_000000000011", -- n=3
|
||||
-- 11 => B"0000_000000000101", -- a=1
|
||||
-- 12 => B"0000_000000000001", -- 1
|
||||
1 => B"00111100001000000000000000000101", --lui $1, 5
|
||||
2 => B"00111100010000000000000000000110", --lui $2, 6
|
||||
3 => B"00111100011000000000000000000000", --lui $3, 0
|
||||
4 => B"00111100100000000000000000000001", --lui $4, 1
|
||||
5 => B"00010000101000000001000000000000", --add $5, $0, $2
|
||||
6 => B"00010000011000110000100000000000", --add $3, $3, $1
|
||||
7 => B"00010100101001010010000000000000", --sub $5, $5, $4
|
||||
8 => B"00110000000000000000000000001010", --jpz end
|
||||
9 => B"00111000000000000000000000000110", --jmp loop
|
||||
10 => B"11111100000000000000000000000000", --hlt
|
||||
|
||||
|
||||
|
||||
others => (others => '0')
|
||||
|
||||
@ -22,49 +22,61 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpupkg.all;
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity RegFile is
|
||||
Port(
|
||||
iClk : in std_logic;
|
||||
iReset : in std_logic;
|
||||
|
||||
icRegAsel : in std_logic_vector(4 downto 0);
|
||||
icRegBsel : in std_logic_vector(4 downto 0);
|
||||
odRegA : out DATA;
|
||||
odRegB : out DATA;
|
||||
|
||||
|
||||
icRegINsel : in std_logic_vector(4 downto 0);
|
||||
|
||||
idDataIn : in DATA;
|
||||
idCarryIn : in std_logic;
|
||||
idZeroIn : in std_logic;
|
||||
|
||||
icLoadEn : in std_logic;
|
||||
|
||||
odDataOut : out DATA;
|
||||
odCarryOut : out std_logic;
|
||||
odZeroOut : out std_logic
|
||||
);
|
||||
end RegFile;
|
||||
|
||||
architecture Behavioral of RegFile is
|
||||
|
||||
type registerFileType is array (0 to 31) of DATA;
|
||||
signal registerFile : registerFileType;
|
||||
|
||||
signal sdData : DATA;
|
||||
signal sdCarry : std_logic;
|
||||
signal sdZero : std_logic;
|
||||
begin
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- Execute Transition
|
||||
process(iClk, iReset)
|
||||
begin
|
||||
if (iReset = '1') then
|
||||
sdData <= (others => '0');
|
||||
for i in 31 downto 0 loop
|
||||
registerFile(i) <= (others=>'0');
|
||||
end loop;
|
||||
|
||||
sdCarry <= '0';
|
||||
sdZero <= '0';
|
||||
|
||||
elsif (rising_edge(iClk)) then
|
||||
if (icLoadEn = '1') then
|
||||
sdData <= idDataIn;
|
||||
registerFile(to_integer(unsigned(icRegINsel))) <= idDataIn;
|
||||
sdCarry <= idCarryIn;
|
||||
sdZero <= idZeroIn;
|
||||
|
||||
@ -74,8 +86,9 @@ begin
|
||||
|
||||
end process;
|
||||
|
||||
-- Output
|
||||
odDataOut <= sdData;
|
||||
|
||||
odRegA <= registerFile(to_integer(unsigned(icRegAsel)));
|
||||
odRegB <= registerFile(to_integer(unsigned(icRegBsel)));
|
||||
odCarryOut <= sdCarry;
|
||||
odZeroOut <= sdZero;
|
||||
|
||||
|
||||
@ -113,14 +113,14 @@ begin
|
||||
when decode =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocLoadEn <= '0'; -- do not save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '1'; -- load instruction
|
||||
ocNextPC <= '1'; -- do not increment pc
|
||||
ocAddrSel <= '0'; -- pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exshl =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
@ -129,7 +129,7 @@ begin
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exshr =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
@ -165,79 +165,79 @@ begin
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exadd =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exsub =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exaddc =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exsubc =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exopor =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exopand =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exopxor =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exopnot =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '1'; -- save result
|
||||
ocEnableRAM <= '1'; -- do not put akku on databus
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
ocNextPC <= '0'; -- increment pc
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '0'; -- no ocJump
|
||||
|
||||
when exjpz =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '0'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
@ -246,7 +246,7 @@ begin
|
||||
ocJump <= '1'; -- ocJump
|
||||
|
||||
when exjpc =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '0'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
@ -255,7 +255,7 @@ begin
|
||||
ocJump <= '1'; -- ocJump
|
||||
|
||||
when exjmp =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '0'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
@ -263,7 +263,7 @@ begin
|
||||
ocAddrSel <= '0'; -- no pc on addressbus
|
||||
ocJump <= '1'; -- ocJump
|
||||
when exhlt =>
|
||||
ocRnotWRam <= '1'; -- read from RAM
|
||||
ocRnotWRam <= '0'; -- read from RAM
|
||||
ocLoadEn <= '0'; -- save result
|
||||
ocEnableRAM <= '0'; -- do not put akku on databus
|
||||
ocLoadInstr <= '0'; -- do not load instruction
|
||||
|
||||
Loading…
Reference in New Issue
Block a user