diff --git a/Makefile b/Makefile
index 49a1e56..10cd5c3 100644
--- a/Makefile
+++ b/Makefile
@@ -6,6 +6,10 @@ include $(MAKEFILES_PATH)/Makefile
 
 ifeq ($(BOARD_TARGET), spartan3e)
 	UCF=UCF/spartan3e.ucf
+else
+ifeq ($(BOARD_TARGET), ml505)
+	UCF=UCF/ML505.ucf
+endif
 endif
 
 
diff --git a/Makefile.files b/Makefile.files
index e4e80a7..dea95b7 100644
--- a/Makefile.files
+++ b/Makefile.files
@@ -6,6 +6,10 @@ VHDL_SRC    += src/SOC.vhd
 
 ifeq ($(BOARD_TARGET), spartan3e)
     VHDL_SRC += src/top_spartan3e.vhd
+else
+ifeq ($(BOARD_TARGET), ml505)
+    VHDL_SRC += src/top_ml505.vhd
 else
     VHDL_SRC += src/top_generic.vhd 
+endif
 endif
\ No newline at end of file
diff --git a/UCF/ML505.ucf b/UCF/ML505.ucf
index 4b38205..c713802 100644
--- a/UCF/ML505.ucf
+++ b/UCF/ML505.ucf
@@ -1,18 +1,10 @@
-NET clk  				LOC = C9;	# Taktsignal Taktgenerator
-NET clk_man  			LOC = H18;		# Manuelles Taktsignal �ber Taster button north
+NET icclk  				LOC = L19;	# Taktsignal Taktgenerator
 
-NET reset	  			LOC = N17;		# Reset, Schiebeschalter links
+NET "icClk" TNM_NET        = "CLOCK_MAIN";
+TIMEGRP  "CLOCK_MAIN_GRP"  = "CLOCK_MAIN";
+TIMESPEC "TS_CLOCK_MAIN"   = PERIOD "CLOCK_MAIN_GRP" 5 ns HIGH 50 %;
 
-NET switch(0)				LOC = L13;	# SW0
-NET switch(1)				LOC	= L14;	# SW1
+NET  icReset_n             LOC="E9"; 
 
-NET led(0)				LOC = F12;
-NET led(1)				LOC = E12;
-NET led(2)				LOC = E11;
-NET led(3)				LOC = F11;
-NET led(4)				LOC = C11;
-NET led(5)				LOC = D11;
-NET led(6)				LOC = E9;
-NET led(7)				LOC = F9;
-
-NET "clk_man" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
+NET odRS232             LOC = "AG20" | IOSTANDARD = LVTTL ;
+NET idRS232             LOC = "AG15" | IOSTANDARD = LVTTL ;
\ No newline at end of file
diff --git a/src/top_ml505.vhd b/src/top_ml505.vhd
new file mode 100644
index 0000000..2627507
--- /dev/null
+++ b/src/top_ml505.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.cpupkg.all;
+
+entity top is	
+generic(
+        GEN_SYS_CLK     :   integer := 200000000; --! system clock in HZ
+        GEN_SOC_CLK     :   integer :=  30000000  --! soc clock in HZ
+);												
+port(	icclk			: in std_logic;							-- Taktsignal
+		icreset_n			: in std_logic;							-- Resetsignal
+		
+		odLED           : out std_logic_vector(7 downto 0);
+		
+		odRS232       :   out std_logic;
+		idRS232       :    in std_logic
+		);							
+end top;
+
+architecture arch of top is
+
+   component SOC
+        generic (
+            GEN_SYS_CLK : integer;
+            GEN_SOC_CLK : integer
+        );
+        port (
+            icclk : in std_logic;
+            icreset : in std_logic;
+            odLED : out std_logic_vector ( 7 downto 0 );
+            odRS232 : out std_logic;
+            idRS232 : in std_logic
+        );
+    end component;
+
+	
+    signal scReset  :   std_logic;	
+begin   
+
+    scReset <= not icReset;
+    
+     soc0:entity work.SOC
+     generic map(
+         GEN_SYS_CLK => GEN_SYS_CLK,
+         GEN_SOC_CLK => GEN_SOC_CLK
+     )
+     port map(
+         icclk       => icclk,
+         icreset     => screset,
+         odLED       => odLED,
+         odRS232     => odRS232,
+         idRS232     => idRS232
+     );
+      
+    
+    
+    
+end arch;