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ADD: files from university processor core

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Dominik Meyer 2013-07-02 22:15:26 +02:00
commit 6cb6930f68
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Makefile Normal file
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include .config
#location of Makefiles
MAKEFILES_PATH=/home/dmeyer/Programmieren/Make/Makefiles/
#which FPGA are we synthesizing for ?
FPGA=xc5vlx110t-1-ff1136
#NR of the FPGA in jtag chain
DEVICE_NR=5
SD= NGC/
#which is the TOP Module of the project ?
TOP=HSU_MIPS_SOC
UCF=UCF/xc5vlx110t-1-ff1136.ucf
#is this a partial reconfiguration project
RECONFIGURATION=0
#modelsim vcom Flags
FLAGS = -O0 -rangecheck -check_synthesis +acc=full
#xilinx license server
XILINX_LICENSE=2100@192.168.1.5
#path to Xilinx tools
XILINX_PATH=/home/Xilinx/14.1/ISE_DS/ISE/bin/lin64/
#modelsim license server
MODELSIM_LICENSE=1718@192.168.1.5
#path to modelsim tools
MODELSIM_PATH=/home/modeltech/modelsim/linux_x86_64
# additional parameters for xilinx tools
XILINX_XST=
XILINX_NGDBUILD=
XILINX_MAP=
XILINX_PAR=
XILINX_BITGEN=
# xst file parameters
define XST_PARAMS
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc off
-reduce_control_sets off
-fsm_extract YES
-fsm_encoding Auto
-safe_implementation Yes
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-keep_hierarchy NO
-max_fanout 100000
-bufg 32
-register_duplication YES
-register_balancing No
-optimize_primitives NO
endef
export XST_PARAMS
%/blockRAM.o: %/blockRAM.vhd
@export LM_LICENSE_FILE=$(MODELSIM_LICENSE);$(MODELSIM_PATH)/vcom -ignorevitalerrors -permissive -work work $< | grep -E 'Compiling|Error:|Warning:'
@touch $@
include $(MAKEFILES_PATH)/Makefile

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VHDL_SRC += src/simpleSOC.vhd
VHDL_SRC += General/ClkEnable.vhd General/clkDivider.vhd
VHDL_PKG +=
VHDL_TB += src/TB/TBsmallTop.vhd

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Modules += UART src/mipsCore src/bramMem src/uart4prhs

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:27 05/10/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port(
idOperand1 : in DATA;
idOperand2 : in DATA;
idCarryIn : in std_logic;
idImmidiate : in DATA;
odResult : out DATA;
odCarryOut : out std_logic;
odZeroOut : out std_logic;
icOperation : in OPTYPE
);
end ALU;
architecture Behavioral of ALU is
signal sdTempResult, sdOp1, sdOp2 : std_logic_vector(16 downto 0);
begin
sdOp1 <= '0' & idOperand1;
sdOp2 <= '0' & idOperand2;
process (sdOp1, sdOp2, idCarryIn, icOperation)
begin
if (icOperation = shl) then
sdTempResult <= sdOp1(15 downto 0) & "0";
elsif (icOperation = shr) then
sdTempResult <= sdOp1(0) & "0" & sdOp1(15 downto 1);
elsif (icOperation = sto) then
sdTempResult <= (others => '-');
elsif (icOperation = loa) then
sdTempResult <= sdOp2;
elsif (icOperation = li) then
sdTempResult <= idImmidiate;
elsif (icOperation = add) then
sdTempResult <= sdOp1 + sdOp2;
elsif (icOperation = sub) then
sdTempResult <= sdOp1 - sdOp2;
elsif (icOperation = addc) then
sdTempResult <= sdOp1 + sdOp2 + ("0000000000000000" & idCarryIn);
elsif (icOperation = subc) then
sdTempResult <= sdOp1 - sdOp2 - ("0000000000000000" & idCarryIn);
elsif (icOperation = opor) then
sdTempResult <= sdOp1 or sdOp2;
elsif (icOperation = opand) then
sdTempResult <= sdOp1 and sdOp2;
elsif (icOperation = opxor) then
sdTempResult <= sdOp1 xor sdOp2;
elsif (icOperation = opnot) then
sdTempResult <= not sdOp1;
elsif (icOperation = jpz) then
sdTempResult <= (others => '-');
elsif (icOperation = jpc) then
sdTempResult <= (others => '-');
elsif (icOperation = jmp) then
sdTempResult <= (others => '-');
else -- (icOperation = hlt)
sdTempResult <= (others => '-');
end if;
end process;
odResult <= sdTempResult(15 downto 0);
odCarryOut <= sdTempResult(16);
odZeroOut <= '1' when sdTempResult(15 downto 0) = "0000000000000000" else
'0';
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:51:48 05/11/2011
-- Design Name:
-- Module Name: CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is
Port(
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
odAddress : out ADDRESS; --! connection to addressbus
ocEnable : out std_logic; --! enable or disable RAM
ocRnotW : out std_logic --! read/write control
);
end CPU;
architecture Behavioral of CPU is
component Steuerwerk is
port (
iClk : in std_logic; --! iClk signal
iReset : in std_logic; --! iReset signal
icOpCode : in optype; --! icOpCode bus
idCarry : in std_logic; --! carry from register file
idZero : in std_logic; --! zero flag from register file
ocRnotWRam : out std_logic; --! r_notw to RAM
ocLoadEn : out std_logic; --! safe result of alu
ocEnableRAM : out std_logic; --! put akku on databus
ocLoadInstr : out std_logic; --! load instruction control signal
ocNextPC : out std_logic; --! increment pc
ocAddrSel : out std_logic; --! pc on addressbus
ocJump : out std_logic --! do a ocJump
);
end component;
component RegFile is
Port(
iClk : in std_logic;
iReset : in std_logic;
idDataIn : in DATA;
idCarryIn : in std_logic;
idZeroIn : in std_logic;
icLoadEn : in std_logic;
odDataOut : out DATA;
odCarryOut : out std_logic;
odZeroOut : out std_logic
);
end component;
component ALU is
Port(
idOperand1 : in DATA;
idOperand2 : in DATA;
idImmidiate : in DATA;
idCarryIn : in std_logic;
odResult : out DATA;
odCarryOut : out std_logic;
odZeroOut : out std_logic;
icOperation : in OPTYPE
);
end component;
component FetchDecode is
Port(
iClk : in std_logic;
iReset : in std_logic;
idData : in DATA;
icAddrSel : in std_logic;
icLoadInstr : in std_logic;
icJump : in std_logic;
icNextPC : in std_logic;
odAddress : out ADDRESS;
odImmidiate : out DATA;
ocOperation : out OPTYPE
);
end component;
component MemInterface is
Port(
bdDataBus : inout DATA;
odAddress : out ADDRESS;
ocRnotW : out std_logic;
ocEnable : out std_logic;
icBusCtrlCPU : in std_logic;
icRAMEnable : in std_logic;
odDataOutCPU : out DATA;
idDataInCPU : in DATA;
idAddressCPU : in ADDRESS
);
end component;
signal scOpCode : optype;
signal sdCarryRF : std_logic;
signal sdZeroRF : std_logic;
signal scRnotWRam : std_logic;
signal scLoadEn : std_logic;
signal scEnableRAM : std_logic;
signal scLoadInstr : std_logic;
signal scNextPC : std_logic;
signal scAddrSel : std_logic;
signal scJump : std_logic;
signal sdAkkuRes : DATA;
signal sdCarryAkku : std_logic;
signal sdZeroAkku : std_logic;
signal sdDataOut : DATA;
signal sdDataIn : DATA;
signal sdAddress : ADDRESS;
signal sdImmidiate : DATA;
begin
SW : Steuerwerk PORT MAP (
iClk => iClk,
iReset => iReset,
icOpCode => scOpCode,
idCarry => sdCarryRF,
idZero => sdZeroRF,
ocRnotWRam => scRnotWRam,
ocLoadEn => scLoadEn,
ocEnableRAM => scEnableRAM,
ocLoadInstr => scLoadInstr,
ocNextPC => scNextPC,
ocAddrSel => scAddrSel,
ocJump => scJump
);
RF: RegFile PORT MAP(
iClk => iClk,
iReset => iReset,
idDataIn => sdAkkuRes,
idCarryIn => sdCarryAkku,
idZeroIn => sdZeroAkku,
icLoadEn => scLoadEn,
odDataOut => sdDataOut,
odCarryOut => sdCarryRF,
odZeroOut => sdZeroRF
);
Calc : ALU Port MAP(
idOperand1 => sdDataOut,
idOperand2 => sdDataIn,
idImmidiate => sdImmidiate,
idCarryIn => sdCarryRF,
odResult => sdAkkuRes,
odCarryOut => sdCarryAkku,
odZeroOut => sdZeroAkku,
icOperation => scOpCode
);
FaD : FetchDecode PORT MAP(
iClk => iClk,
iReset => iReset,
idData => sdDataIn,
icAddrSel => scAddrSel,
icLoadInstr => scLoadInstr,
icJump => scJump,
icNextPC => scNextPC,
odAddress => sdAddress,
odImmidiate => sdImmidiate,
ocOperation => scOpCode
);
MemIF : MemInterface PORT MAP(
bdDataBus => bdData,
odAddress => odAddress,
ocRnotW => ocRnotW,
ocEnable => ocEnable,
icBusCtrlCPU => scRnotWRam,
icRAMEnable => scEnableRAM,
odDataOutCPU => sdDataIn,
idDataInCPU => sdDataOut,
idAddressCPU => sdAddress
);
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:16:43 05/10/2011
-- Design Name:
-- Module Name: FetchDecode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FetchDecode is
Port(
iClk : in std_logic;
iReset : in std_logic;
idData : in DATA;
icAddrSel : in std_logic;
icLoadInstr : in std_logic;
icJump : in std_logic;
icNextPC : in std_logic;
odAddress : out ADDRESS;
odImmidiate : out DATA;
ocOperation : out OPTYPE
);
end FetchDecode;
architecture Behavioral of FetchDecode is
signal sdPC, sdPC_next : ADDRESS;
signal sdAdr, sdAdr_next : ADDRESS;
signal sdImmidate, sdImmidiate_next : DATA;
signal scOp, scOp_next : OPTYPE;
begin
Transition: process(idData, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp)
begin
-- defaults
sdAdr_next <= sdAdr;
sdPC_next <= sdPC;
scOp_next <= scOp;
sdImmidiate_next <= sdImmidate;
if (icLoadInstr = '1') then
sdAdr_next <= idData(11 downto 0);
sdImmidiate_next <= "0000" & idData(11 downto 0);
case idData(15 downto 12) is
when "0000" => scOp_next <= shl;
when "0001" => scOp_next <= shr;
when "0010" => scOp_next <= sto;
when "0011" => scOp_next <= loa;
when "0100" => scOp_next <= add;
when "0101" => scOp_next <= sub;
when "0110" => scOp_next <= addc;
when "0111" => scOp_next <= subc;
when "1000" => scOp_next <= opor;
when "1001" => scOp_next <= opand;
when "1010" => scOp_next <= opxor;
when "1011" => scOp_next <= opnot;
when "1100" => scOp_next <= jpz;
when "1101" => scOp_next <= jpc;
when "1110" => scOp_next <= jmp;
when "1111" => scOP_next <= li;
when others => scOp_next <= hlt;
end case;
end if;
if (icJump = '1') then
sdPC_next <= sdAdr;
end if;
if (icNextPC = '1') then
sdPC_next <= sdPC + '1';
end if;
end process;
-- Execute Transition
process(iClk, iReset)
begin
if (iReset = '1') then
sdPC <= (others => '0');
sdAdr <= (others => '0');
sdImmidate <= (others=>'0');
scOp <= hlt;
elsif (rising_edge(iClk)) then
sdPC <= sdPC_next;
sdAdr <= sdAdr_next;
scOp <= scOp_next;
sdImmidate <= sdImmidiate_next;
end if;
end process;
-- Output
odAddress <= sdAdr when icAddrSel = '0' and icLoadInstr = '0' else
sdAdr_next when icAddrSel = '0' and icLoadInstr = '1' else
sdPC; -- addr_sel = '1'
ocOperation <= scOp when icLoadInstr = '0' else
scOp_next;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:34 05/11/2011
-- Design Name:
-- Module Name: MemInterface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemInterface is
Port(
bdDataBus : inout DATA;
odAddress : out ADDRESS;
ocRnotW : out std_logic;
ocEnable : out std_logic;
icBusCtrlCPU : in std_logic;
icRAMEnable : in std_logic;
odDataOutCPU : out DATA;
idDataInCPU : in DATA;
idAddressCPU : in ADDRESS
);
end MemInterface;
architecture Behavioral of MemInterface is
begin
ocRnotW <= icBusCtrlCPU;
odAddress <= idAddressCPU;
ocEnable <= icRAMEnable;
odDataOutCPU <= bdDataBus;
bdDataBus <= idDataInCPU when icBusCtrlCPU = '0' else
(others => 'Z');
end Behavioral;

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-------------------------------------------------------
--! @file
--! @brief simple RAM for the IIB2 Akkumulator machine
--! @author Dominik Meyer
--! @email dmeyer@hsu-hh.de
--! @date 2010-11-18
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.cpupkg.all;
--! simple RAM for the IIB2 Akkumulator machine using word addressing
entity RAM is
port (
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
idAddress : in ADDRESS; --! connection to addressbus
icEnable : in std_logic; --! enable or disable RAM
icRnotW : in std_logic --! read/write control
);
end RAM;
architecture arch of RAM is
type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
constant Prog1 : MEMORY := ( --! 4k * 16bit of RAM
0 => B"0011_000000001010", -- loa 10 (n)
1 => B"1100_000000001000", -- jpz 8
2 => B"0101_000000001100", -- sub <1>
3 => B"0010_000000001010", -- sto 10 (n)
4 => B"0011_000000001011", -- loa 11 (a)
5 => B"0100_000000001001", -- add <result>
6 => B"0010_000000001001", -- sto <result>
7 => B"1110_000000000000", -- jmp 0
8 => B"1111_000000000000", -- hlt
9 => B"0000_000000000000", -- result
10 => B"0000_000000000011", -- n=3
11 => B"0000_000000000101", -- a=1
12 => B"0000_000000000001", -- 1
others => (others => '0')
);
signal sRam : MEMORY;
signal tData : DATA;
begin
--! functionality of the RAM
process(iClk, iReset)
begin
if (iReset = '1') then
sRam <= Prog1;
tData <= (others => '0');
elsif (rising_edge(iClk)) then
if (icRnotW = '0' and icEnable = '1') then
sRam(conv_integer(unsigned(idAddress))) <= bdData;
else
tData <= sRam(conv_integer(unsigned(idAddress)));
end if;
end if;
end process;
bdData <= tData when icRnotW = '1' else
(others => 'Z');
end arch;

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library ieee;
use ieee.std_logic_1164.all;
library work;
use work.cpupkg.all;
entity Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
port( clk : in std_logic; -- Taktsignal
reset : in std_logic; -- Resetsignal
data_print_1: out DATA;
data_print_2: out DATA
);
end Rechner;
architecture Struktur of Rechner is
signal DATAbus : std_logic_vector(15 downto 0); -- DATAbus
signal address : std_logic_vector(11 downto 0); -- Adressbus
signal rw_ram : std_logic; -- read/write-Signal RAM
signal enable : std_logic;
component CPU is
Port(
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
odAddress : out std_logic_vector(11 downto 0); --! connection to addressbus
ocEnable : out std_logic; --! enable or disable RAM
ocRnotW : out std_logic --! read/write control
);
end component;
component RAM is
port (
iClk : in std_logic;
iReset : in std_logic;
bdData : inout DATA; --! connection to databus
idAddress : in std_logic_vector(11 downto 0); --! connection to addressbus
icEnable : in std_logic; --! enable or disable RAM
icRnotW : in std_logic --! read/write control
);
end component;
begin
CPU_1: CPU port map(
iClk => clk,
iReset => reset,
bdData => DATAbus,
odAddress => address,
ocEnable => enable,
ocRnotW => rw_ram);
RAM_1: RAM port map(
iClk => clk,
iReset => reset,
bdData => DATAbus,
idAddress => address,
icEnable => enable,
icRnotW => rw_ram);
data_print_1 <= DATAbus; -- Ausgabe des DATAbus auf dem LCD-Display
data_print_2 <= "0000" & address;
end Struktur;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:19 05/10/2011
-- Design Name:
-- Module Name: RegFile - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.cpupkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RegFile is
Port(
iClk : in std_logic;
iReset : in std_logic;
idDataIn : in DATA;
idCarryIn : in std_logic;
idZeroIn : in std_logic;
icLoadEn : in std_logic;
odDataOut : out DATA;
odCarryOut : out std_logic;
odZeroOut : out std_logic
);
end RegFile;
architecture Behavioral of RegFile is
signal sdData : DATA;
signal sdCarry : std_logic;
signal sdZero : std_logic;
begin
-- Execute Transition
process(iClk, iReset)
begin
if (iReset = '1') then
sdData <= (others => '0');
sdCarry <= '0';
sdZero <= '0';
elsif (rising_edge(iClk)) then
if (icLoadEn = '1') then
sdData <= idDataIn;
sdCarry <= idCarryIn;
sdZero <= idZeroIn;
end if;
end if;
end process;
-- Output
odDataOut <= sdData;
odCarryOut <= sdCarry;
odZeroOut <= sdZero;
end Behavioral;

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NET clk LOC = C9; # Taktsignal Taktgenerator
NET clk_man LOC = H18; # Manuelles Taktsignal <20>ber Taster button north
NET reset LOC = N17; # Reset, Schiebeschalter links
NET switch(0) LOC = L13; # SW0
NET switch(1) LOC = L14; # SW1
NET led(0) LOC = F12;
NET led(1) LOC = E12;
NET led(2) LOC = E11;
NET led(3) LOC = F11;
NET led(4) LOC = C11;
NET led(5) LOC = D11;
NET led(6) LOC = E9;
NET led(7) LOC = F9;
NET "clk_man" CLOCK_DEDICATED_ROUTE = FALSE;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.cpupkg.all;
entity SOC is -- Testumgebung f<>r Rechner
port(clk : in std_logic; -- Taktsignal
clk_man : in std_logic; -- manuelles Taktsignal
reset : in std_logic; -- Resetsignal
led : out std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0));
end SOC;
architecture Struktur of SOC is
component Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
port( clk : in std_logic; -- Taktsignal
reset : in std_logic; -- Resetsignal
data_print_1: out DATA;
data_print_2: out DATA); -- Ausgabe
end component Rechner;
component antibeat_device is
port (
button_in : in std_logic; --! the button input, for example the button from an fpga
button_out : out std_logic; --! the button output, for example going to the reset or clk of a processor
counter : in std_logic_vector(31 downto 0); --! the number of clk ticks to wait
clk : in std_logic; --! input clock
reset : in std_logic
);
end component antibeat_device;
signal data_print_1 : std_logic_vector(15 downto 0);
signal data_print_2 : std_logic_vector(15 downto 0);
signal sig_entprellt : std_logic;
signal output : std_logic_vector(15 downto 0);
signal clk_out : std_logic;
begin
-- select what to display on led
led <= --(others => '1') when reset='1' else
output(15 downto 8) when switch(0)='1' else
output(7 downto 0);
output <= data_print_1 when switch(1) = '0' else
data_print_2;
antibeat: antibeat_device
port map(
button_in => clk_man,
button_out => clk_out,
counter => x"019BFCC0",
clk => clk,
reset => reset
);
Rechner_0 : Rechner port map(clk => clk_out,
reset => reset,
data_print_1=> data_print_1,
data_print_2=> data_print_2);
end Struktur;

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-------------------------------------------------------
--! @file
--! @brief the control unit of the IIB2 Akkumulator machine
--! @author Dominik Meyer
--! @email dmeyer@hsu-hh.de
--! @date 2010-11-19
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.cpupkg.all;
entity Steuerwerk is
port (
iClk : in std_logic; --! iClk signal
iReset : in std_logic; --! iReset signal
icOpCode : in optype; --! icOpCode bus
idCarry : in std_logic; --! carry from register file
idZero : in std_logic; --! zero flag from register file
ocRnotWRam : out std_logic; --! r_notw to RAM
ocLoadEn : out std_logic; --! safe result of alu
ocEnableRAM : out std_logic; --! put akku on databus
ocLoadInstr : out std_logic; --! load instruction control signal
ocNextPC : out std_logic; --! increment pc
ocAddrSel : out std_logic; --! pc on addressbus
ocJump : out std_logic --! do a ocJump
);
end Steuerwerk;
architecture arch of Steuerwerk is
type STATES is (load, decode, exshl, exshr, exsto, exloa, exadd, exsub, exaddc, exsubc,
exopor, exopand, exopxor, exopnot, exjpz, exjpc, exjmp, exhlt);
signal sState, sState_next : STATES;
begin
-- switch sStates if needed
sState_change: process(iClk,iReset)
begin
if (iReset = '1') then
sState <= load;
elsif (rising_edge(iClk)) then
sState <= sState_next;
end if;
end process;
calc_sState_next: process(sState, icOpCode, idCarry, idZero)
begin
case sState is
when load =>
sState_next <= decode;
when decode =>
case icOpCode is
when shl => sState_next <= exshl;
when shr => sState_next <= exshr;
when sto => sState_next <= exsto;
when loa => sState_next <= exloa;
when add => sState_next <= exadd;
when sub => sState_next <= exsub;
when addc => sState_next <= exaddc;
when subc => sState_next <= exsubc;
when opand => sState_next <= exopand;
when opor => sState_next <= exopor;
when opxor => sState_next <= exopxor;
when opnot => sState_next <= exopnot;
when jpz => if (idZero = '1') then
sState_next <= exjpz;
else
sState_next <= load;
end if;
when jpc => if (idCarry = '1') then
sState_next <= exjpc;
else
sState_next <= load;
end if;
when jmp => sState_next <= exjmp;
when hlt => sState_next <= exhlt;
end case;
when exhlt => sState_next <= exhlt;
when others => sState_next <= load;
end case;
end process;
--! calculate the output in each sState
calc_output: process(sState)
begin
case sState is
when load =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- do not save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- load instruction
ocNextPC <= '0'; -- do not increment pc
ocAddrSel <= '1'; -- pc on addressbus
ocJump <= '0'; -- no ocJump
when decode =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- do not save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '1'; -- load instruction
ocNextPC <= '1'; -- do not increment pc
ocAddrSel <= '0'; -- pc on addressbus
ocJump <= '0'; -- no ocJump
when exshl =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exshr =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exsto =>
ocRnotWRam <= '0'; -- write to RAM
ocLoadEn <= '0'; -- do not save result
ocEnableRAM <= '1'; -- put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exloa =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exadd =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exsub =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exaddc =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exsubc =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exopor =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exopand =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exopxor =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exopnot =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '1'; -- save result
ocEnableRAM <= '1'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when exjpz =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '1'; -- ocJump
when exjpc =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '1'; -- ocJump
when exjmp =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '1'; -- ocJump
when exhlt =>
ocRnotWRam <= '1'; -- read from RAM
ocLoadEn <= '0'; -- save result
ocEnableRAM <= '0'; -- do not put akku on databus
ocLoadInstr <= '0'; -- do not load instruction
ocNextPC <= '0'; -- increment pc
ocAddrSel <= '0'; -- no pc on addressbus
ocJump <= '0'; -- no ocJump
when others =>
ocRnotWRam <= '-'; -- read from RAM
ocLoadEn <= '-'; -- save result
ocEnableRAM <= '-'; -- do not put akku on databus
ocLoadInstr <= '-'; -- do not load instruction
ocNextPC <= '-'; -- increment pc
ocAddrSel <= '-'; -- no pc on addressbus
ocJump <= '-'; -- no ocJump
end case;
end process;
end arch;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:10 05/11/2011
-- Design Name:
-- Module Name: /home/marcel/Lehre/II-B2/ProzessorPimped/TBRechner.vhd
-- Project Name: SoC
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Rechner
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBRechner IS
END TBRechner;
ARCHITECTURE behavior OF TBRechner IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Rechner
PORT(
clk : IN std_logic;
reset : IN std_logic;
data_print_1 : OUT std_logic_vector(15 downto 0);
data_print_2 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal data_print_1 : std_logic_vector(15 downto 0);
signal data_print_2 : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Rechner PORT MAP (
clk => clk,
reset => reset,
data_print_1 => data_print_1,
data_print_2 => data_print_2
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;

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-------------------------------------------------------
--! @file
--! @brief anti beat device for key buttons on the fpga
--! @author Dominik Meyer
--! @email dmeyer@hsu-hh.de
--! @date 2010-06-22
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--! anti beat device for key buttons on the fpga
--! this anti beat device makes sure that button_in is only transmitted to button_output once every second
entity antibeat_device is
port (
button_in : in std_logic; --! the button input, for example the button from an fpga
button_out : out std_logic; --! the button output, for example going to the reset or clk of a processor
counter : in std_logic_vector(31 downto 0); --! the number of clk ticks to wait
clk : in std_logic; --! input clock
reset : in std_logic
);
end antibeat_device;
architecture arch of antibeat_device is
begin
process(clk,button_in)
variable waiting : integer := 0;
variable running : boolean := false;
begin
if (button_in = '1' and running=false) then
running:=true;
waiting:=0;
button_out <= '1';
elsif (rising_edge(clk)) then
if (running = true) then
waiting := waiting + 1;
end if;
if (waiting> counter and button_in='0') then
running := false;
button_out <= '0';
end if;
end if;
end process;
end arch;

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-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpupkg is
type OPTYPE is (shl, shr, sto, loa, li, add, sub, addc, subc, opor, opand, opxor, opnot, jpz, jpc, jmp, hlt);
subtype DATA is std_logic_vector(15 downto 0);
subtype ADDRESS is std_logic_vector(11 downto 0);
end cpupkg;