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FIX: license and author information, signal name changes

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Dominik Meyer 2013-12-30 15:11:56 +01:00
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src/CPU.vhd
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---------------------------------------------------------------------------------- -------------------------------------------------------
-- Company: --! @file
-- Engineer: --! @brief CPU Core of the Simple Processor Core (Geraffel Processor)
-- --! @author Dominik Meyer/ Marcel Eckert
-- Create Date: 10:51:48 05/11/2011 --! @email dmeyer@federationhq.de
-- Design Name: --! @licence GPLv2
-- Module Name: CPU - Behavioral --! @date unknown
-- Project Name: -------------------------------------------------------
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.all;
library work; library work;
use work.cpupkg.all; use work.cpupkg.all;
-- Uncomment the following library declaration if using --! CPU Core of the Simple Processor Core (Geraffel Processor)
-- arithmetic functions with Signed or Unsigned values --!
--use IEEE.NUMERIC_STD.ALL; --! This Code is based on a processor core used at the Helmut Schmidt University for
--! educational purposes.
-- Uncomment the following library declaration if instantiating --!
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is entity CPU is
Port( port(
iClk : in std_logic; iClk : in std_logic; --! main system clock
iReset : in std_logic; iReset : in std_logic; --! system active high reset
bdData : inout DATA; --! connection to databus bdData : inout DATA; --! connection to databus
odAddress : out ADDRESS; --! connection to addressbus odAddress : out ADDRESS; --! connection to addressbus
ocEnable : out std_logic; --! enable or disable RAM ocEnable : out std_logic; --! enable or disable RAM
ocRnotW : out std_logic --! read/write control ocRnotW : out std_logic --! read/write control
); );
end CPU; end CPU;
architecture Behavioral of CPU is architecture Behavioral of CPU is
component Steuerwerk is component ControlUnit is
port ( port (
iClk : in std_logic; --! iClk signal iClk : in std_logic; --! iClk signal
iReset : in std_logic; --! iReset signal iReset : in std_logic; --! iReset signal
icOpCode : in optype; --! icOpCode bus icOpCode : in optype; --! icOpCode bus
idCarry : in std_logic; --! carry from register file idCarry : in std_logic; --! carry from register file
idZero : in std_logic; --! zero flag from register file idZero : in std_logic; --! zero flag from register file
ocRnotWRam : out std_logic; --! r_notw to RAM ocRnotWRam : out std_logic; --! r_notw to RAM
ocLoadEn : out std_logic; --! safe result of alu ocLoadEn : out std_logic; --! safe result of alu
ocEnableRAM : out std_logic; --! put akku on databus ocEnableRAM : out std_logic; --! put akku on databus
ocLoadInstr : out std_logic; --! load instruction control signal ocLoadInstr : out std_logic; --! load instruction control signal
ocNextPC : out std_logic; --! increment pc ocNextPC : out std_logic; --! increment pc
ocAddrSel : out std_logic; --! pc on addressbus ocAddrSel : out std_logic; --! pc on addressbus
ocJump : out std_logic; --! do a ocJump ocJump : out std_logic; --! do a ocJump
ocPCregister : out std_logic; --! put PC to register File ocPCregister : out std_logic; --! put PC to register File
ocUsePC : out std_logic; --! use Register to fill in the PC ocUsePC : out std_logic; --! use Register to fill in the PC
ocLoad : out std_logic --! put databus to ALU immediate port ocLoad : out std_logic --! put databus to ALU immediate port
); );
end component; end component;
component RegFile is component RegFile is
Port( port(
iClk : in std_logic; iClk : in std_logic;
iReset : in std_logic; iReset : in std_logic;
icRegAsel : in std_logic_vector(4 downto 0); icRegAsel : in std_logic_vector(4 downto 0);
icRegBsel : in std_logic_vector(4 downto 0); icRegBsel : in std_logic_vector(4 downto 0);
odRegA : out DATA; odRegA : out DATA;
odRegB : out DATA; odRegB : out DATA;
icPC : in std_logic; -- select PC as input to RegisterFile icPC : in std_logic; -- select PC as input to RegisterFile
idPC : in DATA; idPC : in DATA;
icRegINsel : in std_logic_vector(4 downto 0); icRegINsel: in std_logic_vector(4 downto 0);
idDataIn : in DATA; idDataIn : in DATA;
idCarryIn : in std_logic; idCarryIn : in std_logic;
idZeroIn : in std_logic; idZeroIn : in std_logic;
icLoadEn : in std_logic; icLoadEn : in std_logic;
odCarryOut : out std_logic; odCarryOut: out std_logic;
odZeroOut : out std_logic odZeroOut : out std_logic
); );
end component; end component;
component ALU is component ALU is
Port( port(
idOperand1 : in DATA; idOperand1 : in DATA;
idOperand2 : in DATA; idOperand2 : in DATA;
idImmidiate : in DATA; idImmidiate : in DATA;
idCarryIn : in std_logic; idCarryIn : in std_logic;
odResult : out DATA; odResult : out DATA;
odCarryOut : out std_logic; odCarryOut : out std_logic;
odZeroOut : out std_logic; odZeroOut : out std_logic;
icOperation : in OPTYPE icOperation : in OPTYPE
); );
end component; end component;
component FetchDecode is component FetchDecode is
Port( port(
iClk : in std_logic; iClk : in std_logic;
iReset : in std_logic; iReset : in std_logic;
idData : in DATA; idData : in DATA;
icAddrSel : in std_logic; icAddrSel : in std_logic;
icLoadInstr : in std_logic; icDecodeInstr : in std_logic;
icJump : in std_logic; icJump : in std_logic;
icNextPC : in std_logic; icNextPC : in std_logic;
idPC : in ADDRESS; idPC : in ADDRESS;
icUsePC : in std_logic; icUsePC : in std_logic;
odPC : out ADDRESS; odPC : out ADDRESS;
odAddress : out ADDRESS; odAddress : out ADDRESS;
odImmidiate : out DATA; odImmidiate : out DATA;
odRegAsel : out std_logic_vector(4 downto 0); odRegAsel : out std_logic_vector(4 downto 0);
odRegBsel : out std_logic_vector(4 downto 0); odRegBsel : out std_logic_vector(4 downto 0);
odRegINsel : out std_logic_vector(4 downto 0); odRegINsel : out std_logic_vector(4 downto 0);
ocOperation : out OPTYPE ocOperation : out OPTYPE
); );
end component; end component;
component MemInterface is component MemInterface is
Port( port(
bdDataBus : inout DATA; bdDataBus : inout DATA;
odAddress : out ADDRESS; odAddress : out ADDRESS;
ocRnotW : out std_logic; ocRnotW : out std_logic;
ocEnable : out std_logic; ocEnable : out std_logic;
icBusCtrlCPU : in std_logic; icBusCtrlCPU : in std_logic;
icRAMEnable : in std_logic; icRAMEnable : in std_logic;
odDataOutCPU : out DATA; odDataOutCPU : out DATA;
idDataInCPU : in DATA; idDataInCPU : in DATA;
idAddressCPU : in ADDRESS idAddressCPU : in ADDRESS
); );
end component; end component;
signal sdPC : DATA; signal sdPC : DATA;
signal scPCregister : std_logic; signal scPCregister : std_logic;
signal scUsePC : std_logic; signal scUsePC : std_logic;
signal sdPCfetch : ADDRESS; signal sdPCfetch : ADDRESS;
signal scLoad : std_logic; signal scLoad : std_logic;
signal scOpCode : optype; signal scOpCode : optype;
signal sdCarryRF : std_logic; signal sdCarryRF : std_logic;
signal sdZeroRF : std_logic; signal sdZeroRF : std_logic;
signal scRnotWRam : std_logic; signal scRnotWRam : std_logic;
signal scLoadEn : std_logic; signal scLoadEn : std_logic;
signal scEnableRAM : std_logic; signal scEnableRAM : std_logic;
signal scLoadInstr : std_logic; signal scLoadInstr : std_logic;
signal scNextPC : std_logic; signal scNextPC : std_logic;
signal scAddrSel : std_logic; signal scAddrSel : std_logic;
signal scJump : std_logic; signal scJump : std_logic;
signal sdAkkuRes : DATA; signal sdAkkuRes : DATA;
signal sdCarryAkku : std_logic; signal sdCarryAkku : std_logic;
signal sdZeroAkku : std_logic; signal sdZeroAkku : std_logic;
signal sdDataIn : DATA; signal sdDataIn : DATA;
signal sdAddress : ADDRESS; signal sdAddress : ADDRESS;
signal sdImmidiate : DATA; signal sdImmidiate : DATA;
signal sdImmidiateALU: DATA; signal sdImmidiateALU : DATA;
signal sdRegAsel : std_logic_vector(4 downto 0); signal sdRegAsel : std_logic_vector(4 downto 0);
signal sdRegBsel : std_logic_vector(4 downto 0); signal sdRegBsel : std_logic_vector(4 downto 0);
signal sdRegINsel : std_logic_vector(4 downto 0); signal sdRegINsel : std_logic_vector(4 downto 0);
signal sdRegA : DATA; signal sdRegA : DATA;
signal sdRegB : DATA; signal sdRegB : DATA;
begin begin
SW : Steuerwerk PORT MAP ( SW : ControlUnit port map (
iClk => iClk, iClk => iClk,
iReset => iReset, iReset => iReset,
icOpCode => scOpCode, icOpCode => scOpCode,
idCarry => sdCarryRF, idCarry => sdCarryRF,
idZero => sdZeroRF, idZero => sdZeroRF,
ocRnotWRam => scRnotWRam, ocRnotWRam => scRnotWRam,
ocLoadEn => scLoadEn, ocLoadEn => scLoadEn,
ocEnableRAM => scEnableRAM, ocEnableRAM => scEnableRAM,
ocLoadInstr => scLoadInstr, ocLoadInstr => scLoadInstr,
ocNextPC => scNextPC, ocNextPC => scNextPC,
ocAddrSel => scAddrSel, ocAddrSel => scAddrSel,
ocJump => scJump, ocJump => scJump,
ocPCregister => scPCregister, ocPCregister => scPCregister,
ocUsePC => scUsePC, ocUsePC => scUsePC,
ocLoad => scLoad ocLoad => scLoad
); );
RF: RegFile PORT MAP(
iClk => iClk,
iReset => iReset,
icRegAsel => sdRegAsel,
icRegBsel => sdRegBsel,
icRegINsel => sdRegINsel,
icPC => scPCregister,
idPC => sdPC,
idDataIn => sdAkkuRes,
idCarryIn => sdCarryAkku,
idZeroIn => sdZeroAkku,
icLoadEn => scLoadEn,
odRegA => sdRegA,
odRegB => sdRegB,
odCarryOut => sdCarryRF,
odZeroOut => sdZeroRF
);
Calc : ALU Port MAP(
idOperand1 => sdRegA,
idOperand2 => sdRegB,
idImmidiate => sdImmidiateALU,
idCarryIn => sdCarryRF,
odResult => sdAkkuRes,
odCarryOut => sdCarryAkku,
odZeroOut => sdZeroAkku,
icOperation => scOpCode
);
sdPC(31 downto 16) <= (others=>'0');
FaD : FetchDecode PORT MAP(
iClk => iClk,
iReset => iReset,
idData => sdDataIn,
icAddrSel => scAddrSel,
icLoadInstr => scLoadInstr,
icJump => scJump,
icNextPC => scNextPC,
odPC => sdPC(15 downto 0),
idPC => sdRegA(15 downto 0),
icUsePC => scUsePC,
odAddress => sdAddress,
odImmidiate => sdImmidiate,
odRegAsel => sdRegAsel,
odRegBsel => sdRegBsel,
odRegINsel => sdRegINsel,
ocOperation => scOpCode
);
MemIF : MemInterface PORT MAP(
bdDataBus => bdData,
odAddress => odAddress,
ocRnotW => ocRnotW,
ocEnable => ocEnable,
icBusCtrlCPU => scRnotWRam,
icRAMEnable => scEnableRAM,
odDataOutCPU => sdDataIn,
idDataInCPU => sdRegA,
idAddressCPU => sdAddress
);
RF : RegFile port map(
sdImmidiateALU <= bdData when scLoad='1' else iClk => iClk,
iReset => iReset,
icRegAsel => sdRegAsel,
icRegBsel => sdRegBsel,
icRegINsel => sdRegINsel,
icPC => scPCregister,
idPC => sdPC,
idDataIn => sdAkkuRes,
idCarryIn => sdCarryAkku,
idZeroIn => sdZeroAkku,
icLoadEn => scLoadEn,
odRegA => sdRegA,
odRegB => sdRegB,
odCarryOut => sdCarryRF,
odZeroOut => sdZeroRF
);
Calc : ALU port map(
idOperand1 => sdRegA,
idOperand2 => sdRegB,
idImmidiate => sdImmidiateALU,
idCarryIn => sdCarryRF,
odResult => sdAkkuRes,
odCarryOut => sdCarryAkku,
odZeroOut => sdZeroAkku,
icOperation => scOpCode
);
sdPC(31 downto 16) <= (others => '0');
FaD : FetchDecode port map(
iClk => iClk,
iReset => iReset,
idData => sdDataIn,
icAddrSel => scAddrSel,
icDecodeInstr => scLoadInstr,
icJump => scJump,
icNextPC => scNextPC,
odPC => sdPC(15 downto 0),
idPC => sdRegA(15 downto 0),
icUsePC => scUsePC,
odAddress => sdAddress,
odImmidiate => sdImmidiate,
odRegAsel => sdRegAsel,
odRegBsel => sdRegBsel,
odRegINsel => sdRegINsel,
ocOperation => scOpCode
);
MemIF : MemInterface port map(
bdDataBus => bdData,
odAddress => odAddress,
ocRnotW => ocRnotW,
ocEnable => ocEnable,
icBusCtrlCPU => scRnotWRam,
icRAMEnable => scEnableRAM,
odDataOutCPU => sdDataIn,
idDataInCPU => sdRegA,
idAddressCPU => sdAddress
);
sdImmidiateALU <= bdData when scLoad = '1' else
sdImmidiate; sdImmidiate;
end Behavioral;
end Behavioral;