FIX: license and author information, signal name changes

src/CPU.vhd

@@ -1,41 +1,27 @@
-----------------------------------------------------------------------------------
+-------------------------------------------------------
--- Company: 
+--! @file 
--- Engineer: 
+--! @brief CPU Core of the Simple Processor Core (Geraffel Processor)
--- 
+--! @author Dominik Meyer/ Marcel Eckert
--- Create Date:    10:51:48 05/11/2011 
+--! @email dmeyer@federationhq.de
--- Design Name: 
+--! @licence GPLv2
--- Module Name:    CPU - Behavioral 
+--! @date unknown
--- Project Name: 
+-------------------------------------------------------
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+    use IEEE.STD_LOGIC_1164.all;
 
 library work;
-use work.cpupkg.all;
+    use work.cpupkg.all;
 
--- Uncomment the following library declaration if using
+--! CPU Core of the Simple Processor Core (Geraffel Processor)
--- arithmetic functions with Signed or Unsigned values
+--! 
---use IEEE.NUMERIC_STD.ALL;
+--! This Code is based on a processor core used at the Helmut Schmidt University for
-
+--! educational purposes.
--- Uncomment the following library declaration if instantiating
+--!
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity CPU is
-	Port(
+    port(
-		iClk			:	in		std_logic;
+        iClk      :     in      std_logic;      --! main system clock
-    	iReset		:	in 	std_logic;
+        iReset    :     in      std_logic;      --! system active high reset
         bdData    :     inout   DATA;           --! connection to databus
         odAddress :     out     ADDRESS;        --! connection to addressbus
         ocEnable  :     out     std_logic;      --! enable or disable RAM
@@ -44,7 +30,7 @@ entity CPU is
 end CPU;
 
 architecture Behavioral of CPU is
-	component Steuerwerk is
+    component ControlUnit is
         port  (
             iClk         : in     std_logic;    --! iClk signal
             iReset       : in     std_logic;    --! iReset signal
@@ -65,7 +51,7 @@ architecture Behavioral of CPU is
     end component;
 
     component RegFile is
-	Port(
+        port(
             iClk      : in      std_logic;
             iReset    : in      std_logic;
 
@@ -77,7 +63,7 @@ architecture Behavioral of CPU is
             icPC      : in      std_logic;   -- select PC as input to RegisterFile
             idPC      : in      DATA;
 
-        icRegINsel      : in  std_logic_vector(4 downto 0);
+            icRegINsel: in      std_logic_vector(4 downto 0);
 
             idDataIn  : in      DATA;
             idCarryIn : in      std_logic;
@@ -85,13 +71,13 @@ architecture Behavioral of CPU is
 
             icLoadEn  : in      std_logic;
 
-        odCarryOut  : out std_logic;
+            odCarryOut: out     std_logic;
             odZeroOut : out     std_logic
         );
     end component;
 
     component ALU is
-	Port(
+        port(
             idOperand1  : in  DATA;
             idOperand2  : in  DATA;
             idImmidiate : in  DATA;
@@ -106,13 +92,13 @@ architecture Behavioral of CPU is
     end component;
 
     component FetchDecode is
-	Port(
+        port(
             iClk   : in  std_logic;
             iReset : in  std_logic;
 
             idData      : in  DATA;
             icAddrSel   : in  std_logic;
-        icLoadInstr : in  std_logic;
+            icDecodeInstr : in  std_logic;
             icJump      : in  std_logic;
             icNextPC    : in  std_logic;
             idPC        : in  ADDRESS;
@@ -129,7 +115,7 @@ architecture Behavioral of CPU is
     end component;
 
     component MemInterface is
-	Port(
+        port(
             bdDataBus : inout     DATA;
             odAddress : out        ADDRESS;
             ocRnotW   : out        std_logic;
@@ -168,7 +154,7 @@ architecture Behavioral of CPU is
     signal sdDataIn       : DATA;
     signal sdAddress      : ADDRESS;
     signal sdImmidiate    : DATA;
-   signal sdImmidiateALU: DATA;
+    signal sdImmidiateALU : DATA;
     signal sdRegAsel      : std_logic_vector(4 downto 0);
     signal sdRegBsel      : std_logic_vector(4 downto 0);
     signal sdRegINsel     : std_logic_vector(4 downto 0);
@@ -177,7 +163,7 @@ architecture Behavioral of CPU is
 
 begin
 
-	SW	: Steuerwerk PORT MAP (
+    SW : ControlUnit port map (
         iClk         => iClk,
         iReset       => iReset,
         icOpCode     => scOpCode,
@@ -195,7 +181,7 @@ begin
         ocLoad       => scLoad
     );
 
-	RF: RegFile PORT MAP(
+    RF : RegFile port map(
         iClk   => iClk,
         iReset => iReset,
 
@@ -218,7 +204,7 @@ begin
         odZeroOut  => sdZeroRF
     );
 
-	Calc : ALU Port MAP(
+    Calc : ALU port map(
         idOperand1  => sdRegA,
         idOperand2  => sdRegB,
         idImmidiate => sdImmidiateALU,
@@ -232,14 +218,14 @@ begin
     );
 
 
-	sdPC(31 downto 16) <= (others=>'0');
+    sdPC(31 downto 16) <= (others => '0');
-	FaD : FetchDecode PORT MAP(
+    FaD : FetchDecode port map(
         iClk   => iClk,
         iReset => iReset,
 
         idData      => sdDataIn,
         icAddrSel   => scAddrSel,
-			icLoadInstr	=> scLoadInstr,
+        icDecodeInstr => scLoadInstr,
         icJump      => scJump,
         icNextPC    => scNextPC,
 
@@ -254,7 +240,7 @@ begin
         ocOperation => scOpCode
     );
 
-	MemIF : MemInterface PORT MAP(
+    MemIF : MemInterface port map(
         bdDataBus => bdData,
         odAddress => odAddress,
         ocRnotW   => ocRnotW,
@@ -268,8 +254,7 @@ begin
     );
 
 
-    sdImmidiateALU  <= bdData when scLoad='1' else
+    sdImmidiateALU <= bdData when scLoad = '1' else
                        sdImmidiate;
 
 end Behavioral;
-