ADD: added load immidiate instruction, added UART sources

Makefile

@@ -3,7 +3,7 @@ include .config
 MAKEFILES_PATH=/home/dmeyer/Programmieren/Make/Makefiles/
 
 #which FPGA are we synthesizing for ?
-FPGA=xc5vlx110t-1-ff1136
+FPGA=xc5vlx110t-3-ff1136
 
 #NR of the FPGA in jtag chain
 DEVICE_NR=5
@@ -11,8 +11,8 @@ DEVICE_NR=5
 SD= NGC/
 
 #which is the TOP Module of the project ?
-TOP=HSU_MIPS_SOC
+TOP=SOC
-UCF=UCF/xc5vlx110t-1-ff1136.ucf
+UCF=UCF/xc5vlx110t-3-ff1136.ucf
 
 #is this a partial reconfiguration project 
 RECONFIGURATION=0

Makefile.files

@@ -1,4 +1,4 @@
-VHDL_SRC	+= src/simpleSOC.vhd
+VHDL_PKG   	+= src/cpupkg.vhd
-VHDL_SRC	+= General/ClkEnable.vhd General/clkDivider.vhd
+VHDL_TB		+= src/Rechner.vhd
-VHDL_PKG   	+=  
+VHDL_SRC	+= src/RegFile.vhd src/CPU.vhd src/MemInterface.vhd src/antibeat_device.vhd src/FetchDecode.vhd src/ALU.vhd src/RAM.vhd 
-VHDL_TB		+= src/TB/TBsmallTop.vhd
+VHDL_SRC	+= src/SOC.vhd src/Steuerwerk.vhd

Makefile.modules

@@ -1 +1 @@
-Modules += UART src/mipsCore src/bramMem src/uart4prhs
+Modules += src/UART 

src/ALU.vhd

@@ -53,7 +53,7 @@ begin
 	sdOp1 <= '0' & idOperand1;
 	sdOp2 <= '0' & idOperand2;
 
-	process (sdOp1, sdOp2, idCarryIn, icOperation)
+	process (sdOp1, sdOp2, idCarryIn, icOperation, idImmidiate)
 	begin
 		if (icOperation = shl) then
 			sdTempResult <= sdOp1(15 downto 0) & "0"; 
@@ -67,7 +67,7 @@ begin
 		elsif (icOperation = loa) then
 			sdTempResult <= sdOp2;
 		elsif (icOperation = li) then
-		    sdTempResult <= idImmidiate;
+		    sdTempResult <= '0' & idImmidiate;
 		elsif (icOperation = add) then
 			sdTempResult <= sdOp1 + sdOp2;
 			

src/FetchDecode.vhd

@@ -58,7 +58,7 @@ architecture Behavioral of FetchDecode is
 	signal scOp, scOp_next 		: OPTYPE;
 	
 begin
-	Transition: process(idData, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp)
+	Transition: process(idData, sdImmidate, icLoadInstr, icJump, icNextPC, sdAdr, sdPC, scOp)
 	begin
 		-- defaults
 		sdAdr_next <= sdAdr;

src/Steuerwerk.vhd

@@ -33,7 +33,7 @@ end Steuerwerk;
 
 architecture arch of Steuerwerk is
 
-type STATES	is (load, decode, exshl, exshr, exsto, exloa, exadd, exsub, exaddc, exsubc, 
+type STATES	is (load, decode, exshl, exshr, exsto, exloa, exli, exadd, exsub, exaddc, exsubc, 
 					exopor, exopand, exopxor, exopnot, exjpz, exjpc, exjmp, exhlt);
 
 signal sState, sState_next	:	STATES;
@@ -64,6 +64,7 @@ begin
 							when shr	=>		sState_next <= exshr;
 							when sto	=>  	sState_next <= exsto;
 							when loa	=>		sState_next <= exloa;
+							when li     =>      sState_next <= exli;
 							when add	=>  	sState_next <= exadd;
 							when sub	=>  	sState_next <= exsub;
 							when addc =>  	sState_next <= exaddc;

src/UART/Fifo.vhd

@@ -0,0 +1,88 @@
+--------------------------------------------------------------------------------
+-- Entity: Fifo
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : Fifo.vhd
+-- Creation date     : 2011-05-27
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : <short description>
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-27   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity Fifo is
+	port  (
+		iReset		: in  std_logic;
+		
+		iClkWrite 	: in  std_logic; 
+		icWriteEn	: in  std_logic;
+		
+		iClkRead 	: in  std_logic; 
+		icReadEn	: in  std_logic;
+		
+		idDataIn	: in  std_logic_vector(8 downto 0);
+		odDataOut	: out std_logic_vector(8 downto 0);
+		
+		ocEmpty		: out std_logic;
+		ocFull		: out std_logic;
+		
+		ocAlmostE	: out std_logic;
+		ocAlmostF	: out std_logic
+	);
+end Fifo;
+
+architecture arch of Fifo is
+	signal sdDataOut : std_logic_vector(31 downto 0);
+	signal sdDataIn	 : std_logic_vector(31 downto 0);
+	signal sdParityIN: std_logic_vector(3 downto 0);
+	signal sdParityOut:std_logic_vector(3 downto 0);
+begin
+
+	 FIFO36_inst : FIFO36
+	   generic map (
+	      ALMOST_FULL_OFFSET 	=> X"0080", -- Sets almost full threshold
+	      ALMOST_EMPTY_OFFSET 	=> X"0080", -- Sets the almost empty threshold
+	      DATA_WIDTH			=> 9,    	-- Sets data width to 4, 9, 18, or 36
+	      DO_REG 				=> 1,       -- Enable output register ( 0 or 1)
+	                                      	-- Must be 1 if the EN_SYN = FALSE
+	      EN_SYN 				=> FALSE,   -- Specified FIFO as Asynchronous (FALSE) or 
+	                                      	-- Synchronous (TRUE)
+	      FIRST_WORD_FALL_THROUGH => TRUE, 	-- Sets the FIFO FWFT to TRUE or FALSE
+	      SIM_MODE 				=> "FAST") 	-- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation
+	                          				-- Design Guide" for details
+	   port map (
+	      ALMOSTEMPTY 	=> ocAlmostE, 	-- 1-bit almost empty output flag
+	      ALMOSTFULL	=> ocAlmostF,	-- 1-bit almost full output flag
+	      DO 			=> sdDataOut, 	-- 32-bit data output
+	      DOP 			=> sdParityOut, -- 4-bit parity data output
+	      EMPTY 		=> ocEmpty,		-- 1-bit empty output flag
+	      FULL 			=> ocFull,		-- 1-bit full output flag
+	      RDCOUNT 		=> open,		-- 13-bit read count output
+	      RDERR 		=> open,		-- 1-bit read error output
+	      WRCOUNT 		=> open,		-- 13-bit write count output
+	      WRERR 		=> open,		-- 1-bit write error
+	      DI 			=> sdDataIn,	-- 32-bit data input
+	      DIP 			=> sdParityIn,  -- 4-bit parity input
+	      RDCLK 		=> iClkRead,	-- 1-bit read clock input
+	      RDEN 			=> icReadEn,	-- 1-bit read enable input
+	      RST 			=> iReset,		-- 1-bit reset input
+	      WRCLK 		=> iClkWrite,	-- 1-bit write clock input
+	      WREN 			=> icWriteEn    -- 1-bit write enable input
+	   );
+	   
+	   odDataOut(8 downto 1) <= sdDataOut(7 downto 0);
+	   odDataOut(0)          <= sdParityOut(0); 
+	   sdDataIn <= X"000000" & idDataIn(8 downto 1);
+	   sdParityIN  <= "000" & idDataIn(0);
+end arch;
+

src/UART/FifoS3e.vhd

@@ -0,0 +1,78 @@
+--------------------------------------------------------------------------------
+-- Entity: Fifo
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : Fifo.vhd
+-- Creation date     : 2011-05-27
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : <short description>
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-27   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity Fifo is
+	port  (
+		iReset		: in  std_logic;
+		
+		iClkWrite 	: in  std_logic; 
+		icWriteEn	: in  std_logic;
+		
+		iClkRead 	: in  std_logic; 
+		icReadEn	: in  std_logic;
+		
+		idDataIn	: in  std_logic_vector(7 downto 0);
+		odDataOut	: out std_logic_vector(7 downto 0);
+		
+		ocEmpty		: out std_logic;
+		ocFull		: out std_logic;
+		
+		ocAlmostE	: out std_logic;
+		ocAlmostF	: out std_logic
+	);
+end Fifo;
+
+architecture arch of Fifo is
+    component fifo_generator_v7_2
+        port (
+        rst: in std_logic;
+        wr_clk: in std_logic;
+        rd_clk: in std_logic;
+        din: in std_logic_vector(7 downto 0);
+        wr_en: in std_logic;
+        rd_en: in std_logic;
+        dout: out std_logic_vector(7 downto 0);
+        full: out std_logic;
+        almost_full: out std_logic;
+        empty: out std_logic;
+        almost_empty: out std_logic);
+    end component;
+	
+begin
+
+	fifo_generator_v7_2_0 : fifo_generator_v7_2
+  		port map (		
+    		rst 		=> iReset,
+		    wr_clk 		=> iClkWrite,
+		    rd_clk 		=> iClkRead,
+		    din 		=> idDataIn,
+		    wr_en 		=> icWriteEn,
+		    rd_en 		=> icReadEn,
+		    dout 		=> odDataOut,
+		    full 		=> ocFull,
+		    almost_full => ocAlmostF,
+		    empty 		=> ocEmpty,
+		    almost_empty => ocAlmostE
+  	);
+	 
+end arch;
+

src/UART/FifoS6.vhd

@@ -0,0 +1,79 @@
+--------------------------------------------------------------------------------
+-- Entity: Fifo
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : Fifo.vhd
+-- Creation date     : 2011-05-27
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : <short description>
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-27   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity Fifo is
+	port  (
+		iReset		: in  std_logic;
+		
+		iClkWrite 	: in  std_logic; 
+		icWriteEn	: in  std_logic;
+		
+		iClkRead 	: in  std_logic; 
+		icReadEn	: in  std_logic;
+		
+		idDataIn	: in  std_logic_vector(7 downto 0);
+		odDataOut	: out std_logic_vector(7 downto 0);
+		
+		ocEmpty		: out std_logic;
+		ocFull		: out std_logic;
+		
+		ocAlmostE	: out std_logic;
+		ocAlmostF	: out std_logic
+	);
+end Fifo;
+
+architecture arch of Fifo is
+	component FifoS6 IS
+  		PORT (
+		    wr_clk : IN STD_LOGIC;
+    		rst : IN STD_LOGIC;
+		    rd_clk : IN STD_LOGIC;
+		    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		    wr_en : IN STD_LOGIC;
+		    rd_en : IN STD_LOGIC;
+		    dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		    full : OUT STD_LOGIC;
+		    almost_full : OUT STD_LOGIC;
+		    empty : OUT STD_LOGIC;
+		    almost_empty : OUT STD_LOGIC
+  	);
+	END component;
+	
+begin
+
+	FifoS6_0 : FifoS6
+  		port map (		
+    		rst 		=> iReset,
+		    wr_clk 		=> iClkWrite,
+		    rd_clk 		=> iClkRead,
+		    din 		=> idDataIn,
+		    wr_en 		=> icWriteEn,
+		    rd_en 		=> icReadEn,
+		    dout 		=> odDataOut,
+		    full 		=> ocFull,
+		    almost_full => ocAlmostF,
+		    empty 		=> ocEmpty,
+		    almost_empty => ocAlmostE
+  	);
+	 
+end arch;
+

src/UART/Makefile.files

@@ -0,0 +1,14 @@
+ifeq ($(FPGA_FAMILY),spartan6)
+	VHDL_SRC	+= FifoS6.vhd
+else
+ifeq ($(FPGA_FAMILY),spartan3e)
+	VHDL_SRC        += FifoS3e.vhd
+else
+	VHDL_SRC	+= Fifo.vhd
+endif
+endif
+
+
+VHDL_SRC	+= Receiver.vhd ReceiverAndFifo.vhd Sender.vhd SenderAndFifo.vhd UART.vhd          
+VHDL_PKG        +=
+VHDL_TB		+=

src/UART/Receiver.vhd

@@ -0,0 +1,115 @@
+--------------------------------------------------------------------------------
+-- Entity: Receiver
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : Receiver.vhd
+-- Creation date     : 2011-05-25
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : implements an RS232 Receiver
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-25   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! brief
+--! implements an RS232 Receiver
+
+--! detailed
+--! implements an RS232 Receiver, 8 Bits, no parity check and no Stop Bits
+--! sending parities or stop bits should not produce errors
+entity Receiver is
+    Port ( 
+    	iSysClk    : in  std_logic;                    
+        ie4BaudClkEn : in  std_logic;reset 		: in std_logic;			--! signal description asynchronous reset
+        Rx 			: in  STD_LOGIC;		--! signal description signal for the RS232 Rx line
+        data 		: out STD_LOGIC_VECTOR (7 downto 0);	--! signal description last data received
+        parity      : out std_logic;                        --! signal description
+        icEnableParity: in std_logic;                       --! signal description Enable reception of the parity bit 
+		ready 		: out STD_LOGIC);		--! '0' signals receving in progress, if '1' after a previous '0' signals data available at <data> 
+end Receiver;
+
+architecture Behavioral of Receiver is
+	signal z, tz : integer range 0 to 63;
+	signal result, tresult : STD_LOGIC_VECTOR(7 downto 0);
+    signal sdParity : std_logic;
+begin
+	process (z, Rx, icEnableParity)
+	begin
+			if z = 0 then
+				if (Rx ='0') then
+					tz <= 1;
+				else
+					tz <= 0;
+				end if;
+				
+			elsif z <= 36 then
+				tz <= z + 1;
+			elsif (z <= 40 and icEnableParity='1') then
+			     tz <= z+1;		
+			else
+				tz <= 0;		
+
+			end if;
+	end process;
+	
+	tresult <= Rx & result(7 downto 1);	
+	
+	process (iSysClk)
+	begin
+		if (iSysClk'event and iSysClk = '1') then
+		  if reset = '1' then
+            z <= 0;
+            sdParity    <= '0';
+          elsif ie4BaudClkEn = '1' then
+			z <= tz;
+			case z is
+					
+				when 5 =>
+					result <= tresult;		-- D(0)
+					
+				when 9 =>
+					result <= tresult;		-- D(1)
+					
+				when 13 =>
+					result <= tresult;		-- D(2)
+
+				when 17 =>
+					result <= tresult;		-- D(3)
+
+				when 21 =>
+					result <= tresult;		-- D(4)
+				
+				when 25 =>
+					result <= tresult;		-- D(5)
+					
+				when 29 =>
+					result <= tresult;		-- D(6)
+					
+				when 33 =>
+					result <= tresult;		-- D(7)
+				
+				when 37 =>
+				    result  <= result;
+				    if (icEnableParity='1') then
+				        sdParity <= Rx;
+				    else
+				        sdParity <= '0';
+				    end if;	
+				-- optional TODO: add check for STOP-Bit(s) 
+					
+				when others => result <= result;
+			end case;
+		  end if;
+		end if;
+	end process;
+    
+    parity <= sdParity;
+	data <= result;
+	ready <= '1' when z = 0 else '0';
+	
+end Behavioral;
+

src/UART/ReceiverAndFifo.vhd

@@ -0,0 +1,179 @@
+--------------------------------------------------------------------------------
+-- Entity: ReceiverAndFifo
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : ReceiverAndFifo.vhd
+-- Creation date     : 2011-05-31
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : implements an RS232 Receiver with additional Fifo
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-31   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+--! brief
+--! implements an RS232 Receiver with additional Fifo
+
+--! detailed
+--! implements an RS232 Receiver with additonal Fifo (8 Bit data width, 4k data depth)
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity ReceiverAndFifo is
+   
+	port  (
+		iSysClk 	  : in  std_logic;						--! signal description System side clock
+		ieClkEn       : in  std_logic;
+		ie4xBaudClkEn : in  std_logic;      				--! signal description UART clock (4xBAUD Rate frequency!)
+		iReset		  : in  std_logic;						--! signal description asynchronous reset
+	    icEnableParity: in  std_logic;                      --! signal description allow reception of parity bit	
+		odDataRcvd	  : out  std_logic_vector(7 downto 0);	--! signal description data from Fifo
+		odParity      : out  std_logic;                       --! possible parity bit
+		ocREmpty	  : out std_logic;						--! signal description indicates that Fifo is empty
+		ocRFull		  : out std_logic;						--! signal description indicates that Fifo is full
+		ocRAlmostE	  : out std_logic;						--! signal description indicates that Fifo is empty to half full
+		ocRAlmostF	  : out std_logic;						--! signal description indicates that Fifo is half full to full
+		icRReadEn	  : in  std_logic;						--! signal description get next value from Fifo (Fifo is in First Word Fall Through Mode!)
+		idReceive	  : in  std_logic							--! signal description signal for the RS232 Tx line
+	);
+end ReceiverAndFifo;
+
+architecture arch of ReceiverAndFifo is
+
+	component Receiver is
+	    port ( 
+	    	iSysClk       : in  std_logic;                    
+            ie4BaudClkEn  : in  std_logic;
+	    	reset 	      : in  STD_LOGIC;
+	        Rx 		      : in  STD_LOGIC;
+	        data 	      : out STD_LOGIC_VECTOR (7 downto 0);
+	        parity        : out std_logic;
+	        icEnableParity: in  std_logic;
+			ready 	      : out STD_LOGIC);
+	end component;
+	
+	component Fifo is
+		port  (
+			iReset		: in  std_logic;
+			
+			iClkWrite 	: in  std_logic; 
+			icWriteEn	: in  std_logic;
+			
+			iClkRead 	: in  std_logic; 
+			icReadEn	: in  std_logic;
+			
+			idDataIn	: in  std_logic_vector(8 downto 0);
+			odDataOut	: out std_logic_vector(8 downto 0);
+			
+			ocEmpty		: out std_logic;
+			ocFull		: out std_logic;
+			
+			ocAlmostE	: out std_logic;
+			ocAlmostF	: out std_logic
+		);
+	end component;
+
+    signal scRWrite         : std_logic;
+	signal scRWriteEn 		: std_logic;
+	signal seRReadEn        : std_logic;
+	signal sdDataRcvd		: STD_LOGIC_VECTOR (8 downto 0);
+	signal sdParity         : std_logic;
+	
+	signal scRcvrEmpty		: std_logic;
+	signal scRcvrFull		: std_logic;
+	signal scRcvrAEmpty		: std_logic;
+	signal scRcvrAFull		: std_logic;
+	signal scReaderReady	: std_logic;
+	
+	type ReceiverCtrlType is (RCVR_WAITING, RCVR_RCV, RCVR_READY);
+	signal sRCVRCtrlState : ReceiverCtrlType;
+	
+begin
+    scRWriteEn <= scRWrite and ie4xBaudClkEn;
+    seRReadEn <= icRReadEn and ieClkEn;
+    
+	rcvFifo : Fifo
+					PORT MAP(
+						iReset		=> iReset,
+			
+						iClkWrite 	=> iSysClk,
+						icWriteEn	=> scRWriteEn,
+						
+						iClkRead 	=> iSysClk,
+						icReadEn	=> seRReadEn,
+						
+						idDataIn	=> sdDataRcvd,
+						odDataOut(8 downto 1)	=> odDataRcvd,
+					    odDataOut(0)            => odParity,
+						
+						ocEmpty		=> scRcvrEmpty,
+						ocFull		=> scRcvrFull,
+						
+						ocAlmostE	=> scRcvrAEmpty,
+						ocAlmostF	=> scRcvrAFull
+					);
+
+	ocREmpty	<= scRcvrEmpty;
+	ocRFull		<= scRcvrFull;
+	ocRAlmostE	<= scRcvrAEmpty;
+	ocRAlmostF	<= scRcvrAFull;
+	
+	RS232Receiver : Receiver
+						port map( 
+						    iSysClk    => iSysClk,              
+                            ie4BaudClkEn => ie4xBaudClkEn,
+					    	reset	=> iReset, 
+					        Rx 		=> idReceive,
+					        data 	=> sdDataRcvd(8 downto 1),
+					        parity  => sdDataRcvd(0),
+					        icEnableParity => icEnableParity,
+							ready 	=> scReaderReady
+						);
+	
+	
+	ReceiverCtrl : process (iSysClk)
+    begin
+        if (rising_edge(iSysClk)) then
+		  if (iReset = '1') then
+            sRCVRCtrlState    <= RCVR_WAITING;
+        
+          elsif ie4xBaudClkEn = '1' then
+            
+            case sRCVRCtrlState is
+                when RCVR_WAITING  => 
+                    if scReaderReady = '0' then
+                        sRCVRCtrlState <= RCVR_RCV;
+                    end if;
+            
+                when RCVR_RCV =>
+                    if scReaderReady = '1' then
+                        sRCVRCtrlState <= RCVR_READY;
+                    end if;
+            
+                when RCVR_READY =>
+                    sRCVRCtrlState <= RCVR_WAITING;
+                
+            end case;
+            
+--            if (sRCVRCtrlState = RCVR_WAITING and scReaderReady = '0' ) then
+--              sRCVRCtrlState <= RCVR_RCV;
+--          
+--          elsif (sRCVRCtrlState = RCVR_RCV and scReaderReady = '1') then
+--              sRCVRCtrlState <= RCVR_READY;
+--          
+--          elsif (sRCVRCtrlState <= RCVR_READY) then
+--              sRCVRCtrlState <= RCVR_WAITING;
+--              
+--          end if;
+	       end if;
+		end if;
+		
+	end process;
+	
+	scRWrite <= 	'1' when sRCVRCtrlState = RCVR_READY else
+					'0';
+
+end arch;
+

src/UART/Sender.vhd

@@ -0,0 +1,125 @@
+--------------------------------------------------------------------------------
+-- Entity: Sender
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : Sender.vhd
+-- Creation date     : 2011-05-25
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : implements an RS232 Sender
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-25   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! brief
+--! implements an RS232 Sender
+
+--! detailed
+--! implements an RS232 Sender, 8 Bits without parity and 2 Stop Bits
+entity Sender is
+    port ( 	
+            iSysClk     : in  std_logic;                        --! signal description System side clock
+            ieBaudClkEn : in  std_logic;                        --! signal description clock enable signal for needed BAUD rate 
+    		iReset		: in  STD_LOGIC;						--! signal description synchronous reset
+           	icSend 		: in  STD_LOGIC;						--! signal description force a send of <idData>
+           	idData 		: in  STD_LOGIC_VECTOR (7 downto 0);	--! signal description the data to be sent
+           	idParity    : in  std_logic;                        --! signal description the parity bit of the data
+           	icEnableParity:in std_logic;                        --! signal description enable sending of the parity bit
+          	odTransmit 	: out  STD_LOGIC;						--! signal description signal for the RS232 Tx line
+			ocReady		: out  STD_LOGIC;						--! signal description signals availability of the Sender (no Sending in Progress)
+			ocSyn		: out  STD_LOGIC);						--! signal description signals sending of first Stop Bit 
+end Sender;
+
+architecture Behavioral of Sender is
+	signal temp, tnext  :STD_LOGIC_VECTOR(12 downto 0);
+	
+	type StateType is (WAITING, INIT, HIGH, START, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, PARITY, STOP1, STOP2);
+	signal state : StateType;
+begin
+	process(iSysClk)
+	begin
+		if (iSysClk'event and iSysClk = '1') then
+			if (iReset = '1') then
+                temp <= (others => '1');
+                state <= WAITING;
+                odTransmit <= '1';
+                ocSyn <= '0';
+        
+            elsif ieBaudClkEn = '1' then 
+    			temp <= tnext;
+    			odTransmit <= temp(0);
+    			case state is
+    				when WAITING => 
+    					if (icSend = '1') then
+    					   if (icEnableParity = '1') then
+    					    temp <= "11" & idParity & idData &  "01";
+    					   else
+    						temp <= "111" & idData & "01";
+    					   end if;
+    						state <= INIT;
+    					else
+    						state <= WAITING;
+    					end if;
+    				
+    				when INIT =>
+    					state <= HIGH;
+    				
+    				when HIGH => 
+    					state <= START;
+    				
+    				when START =>
+    					state <= DATA0;
+    					
+    				when DATA0 =>
+    					state <= DATA1;
+    					
+    				when DATA1 =>
+    					state <= DATA2;
+    					
+    				when DATA2 =>
+    					state <= DATA3;
+    					
+    				when DATA3 =>
+    					state <= DATA4;
+    				
+    				when DATA4 =>
+    					state <= DATA5;
+    					
+    				when DATA5 =>
+    					state <= DATA6;
+    				
+    				when DATA6 =>
+    					state <= DATA7;
+    					
+    				when DATA7 =>
+    				    if (icEnableParity = '1') then
+    				        state <= PARITY;
+    				    else
+    					   state <= STOP1;
+    					end if;
+    					
+    			    when PARITY  =>
+    			         state <= STOP1;
+    				
+    				when STOP1 =>
+    					state <= STOP2;
+    					ocSyn <= '1';
+    					
+    				when STOP2 =>
+    					state <= WAITING;
+    					ocSyn <= '0';
+    			end case;
+    		end if;
+		end if;
+	end process;
+
+	tnext <= '1' & temp(12 downto 1);
+	ocReady <= '1' when state = WAITING else
+				'0';
+	
+end Behavioral;
+

src/UART/SenderAndFifo.vhd

@@ -0,0 +1,196 @@
+--------------------------------------------------------------------------------
+-- Entity: SenderAndFifo
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : SenderAndFifo.vhd
+-- Creation date     : 2011-05-31
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : implements an RS232 Sender with additional Fifo
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-31   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+
+
+--! brief
+--! implements an RS232 Sender with additional Fifo
+
+--! detailed
+--! implements an RS232 Sender with additonal Fifo (8 Bit data width, 4k data depth)
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity SenderAndFifo is
+	port  (
+		iSysClk 	: in  std_logic;					--! signal description System side clock
+		ieClkEn     : in  std_logic;
+		ieBaudClkEn	: in  std_logic;					--! signal description UART clock (BAUD Rate frequency!)
+		iReset		: in  std_logic;					--! signal description asynchronous reset
+		
+		icSend		: in  std_logic;					--! signal description add data <idDataSend> to Fifo (Enable Signal)
+		idDataSend	: in  std_logic_vector(7 downto 0); --! signal description data to be added to the Fifo
+		idParity    : in  std_logic;                    --! signal description the parity bit for the data
+		icEnableParity: in std_logic;                   --! signal description enable the sending of the parity bit
+		ocSEmpty	: out std_logic;					--! signal description indicates that Fifo is empty
+		ocSFull		: out std_logic;					--! signal description indicates that Fifo is full
+		ocSAlmostE	: out std_logic;					--! signal description indicates that Fifo is empty to half full
+		ocSAlmostF	: out std_logic;					--! signal description indicates that Fifo is half full to full
+		
+		odTransmit	: out std_logic						--! signal description signal for the RS232 Tx line
+	);
+end SenderAndFifo;
+
+architecture arch of SenderAndFifo is
+	component Sender is
+	    port ( 	
+	    	iSysClk    : in  std_logic;                    
+            ieBaudClkEn : in  std_logic;
+    		iReset		: in  STD_LOGIC;
+           	icSend 		: in  STD_LOGIC;
+           	idData 		: in  STD_LOGIC_VECTOR (7 downto 0);
+           	idParity    : in  std_logic;
+           	icEnableParity:in std_logic;
+          	odTransmit 	: out  STD_LOGIC;
+			ocReady		: out  STD_LOGIC;
+			ocSyn		: out  STD_LOGIC);
+	end component;
+	
+	component Fifo is
+		port  (
+			iReset		: in  std_logic;
+			
+			iClkWrite 	: in  std_logic; 
+			icWriteEn	: in  std_logic;
+			
+			iClkRead 	: in  std_logic; 
+			icReadEn	: in  std_logic;
+			
+			idDataIn	: in  std_logic_vector(8 downto 0);
+			odDataOut	: out std_logic_vector(8 downto 0);
+			
+			ocEmpty		: out std_logic;
+			ocFull		: out std_logic;
+			
+			ocAlmostE	: out std_logic;
+			ocAlmostF	: out std_logic
+		);
+	end component;
+	
+	signal scSenderRead		: std_logic;
+	signal scSenderReadEn   : std_logic;
+	
+	signal sdDataToSend		: STD_LOGIC_VECTOR (8 downto 0);
+	signal scSenderEmpty	: std_logic;
+	signal scSenderFull		: std_logic;
+	signal scSenderAEmpty	: std_logic;
+	signal scSenderAFull	: std_logic;
+	
+	signal scSenderReady	: std_logic;
+	signal scSenderSendReq	: std_logic;
+	signal scSyn			: std_logic;
+	
+	type SenderCtrlType is (SENDER_WAITING, SENDER_SEND, SENDER_SENDING, SENDER_SENDING_SYN);
+	signal sSenderCtrlState : SenderCtrlType;
+	
+	signal seSend : std_logic;
+	
+	signal sdFifoDataIn    :   std_logic_vector(8 downto 0);
+	
+begin
+	
+	scSenderReadEn <= scSenderRead and ieBaudClkEn;
+	seSend         <= icSend and ieClkEn;
+	
+	sendFifo : Fifo
+					PORT MAP(
+						iReset		=> iReset,
+			
+						iClkWrite 	=> iSysClk,
+						icWriteEn	=> seSend,
+						
+						iClkRead 	=> iSysClk,
+						icReadEn	=> scSenderReadEn,
+						
+						idDataIn	=> sdFifoDataIn,
+						odDataOut	=> sdDataToSend,
+						
+						ocEmpty		=> scSenderEmpty,
+						ocFull		=> scSenderFull,
+						
+						ocAlmostE	=> scSenderAEmpty,
+						ocAlmostF	=> scSenderAFull
+					);
+    
+    sdFifoDataIn    <= idDataSend & idParity;
+    
+	ocSEmpty	<= scSenderEmpty;
+	ocSFull		<= scSenderFull;
+	ocSAlmostE	<= scSenderAEmpty;
+	ocSAlmostF	<= scSenderAFull;
+	
+	RS232Sender : Sender
+					PORT MAP(
+						iSysClk     => iSysClk,      
+                        ieBaudClkEn => ieBaudClkEn,
+			    		iReset		=> iReset,
+			           	icSend 		=> scSenderSendReq,
+			           	idData 		=> sdDataToSend(8 downto 1),
+			           	idParity    => sdDataToSend(0),
+			           	icEnableParity=>icEnableParity,
+			          	odTransmit 	=> odTransmit,
+						ocReady		=> scSenderReady,
+						ocSyn		=> scSyn
+					);
+	
+	SenderCtrl : process (iSysClk, iReset, sSenderCtrlState, scSenderReady, ieclken, scsenderempty, scsyn)
+	begin
+		if (rising_edge(iSysClk)) then
+		    if (iReset = '1') then
+                sSenderCtrlState <= SENDER_WAITING;
+        
+            elsif ieClkEn = '1' then
+    			case sSenderCtrlState is 
+    			     when SENDER_WAITING =>
+    			        if scSenderEmpty = '0' then
+    				        sSenderCtrlState <= SENDER_SEND;
+    				    end if;
+    				
+    			     when SENDER_SEND => 
+    			        if scSenderReady = '0' then
+    				        sSenderCtrlState <= SENDER_SENDING;
+    				    end if;
+    		
+    			     when SENDER_SENDING => 
+    			        if scSyn = '1' then
+    			            sSenderCtrlState <= SENDER_SENDING_SYN;
+    			        end if;
+    				
+    			     when SENDER_SENDING_SYN =>
+    			        if scSyn = '0' then
+    				        sSenderCtrlState <= SENDER_WAITING;
+    				    end if;
+    				
+    			end case;
+		    end if;
+		end if;
+		
+		scSenderRead 	<= '0';
+		scSenderSendReq <= '0';
+		
+		if (sSenderCtrlState = SENDER_SEND) then
+			scSenderSendReq <= '1';
+			
+		end if;
+		
+		if (sSenderCtrlState = SENDER_SENDING_SYN) then
+			scSenderRead <= '1';
+		end if;
+	
+	end process;
+
+
+end arch;
+

src/UART/UART.vhd

@@ -0,0 +1,228 @@
+--------------------------------------------------------------------------------
+-- Entity: UART
+--------------------------------------------------------------------------------
+-- Copyright ... 2011
+-- Filename          : UART.vhd
+-- Creation date     : 2011-05-27
+-- Author(s)         : marcel
+-- Version           : 1.00
+-- Description       : <short description>
+--------------------------------------------------------------------------------
+-- File History:
+-- Date         Version  Author   Comment
+-- 2011-05-27   1.00     marcel     Creation of File
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity UART is
+    generic(
+        GEN_SysClockinHz    : integer                       := 33000000;
+        GEN_Baudrate        : integer                       := 115200;       --! Baudrate to use 
+	GEN_HasExternBaudLimit : boolean			    := false
+    );
+	port  (
+		iSysClk 	: in  std_logic;
+		ieClkEn     : in  std_logic;
+		iReset		: in  std_logic;
+
+		icBaudLExt   : in  integer := 0;
+		icEnableParity : in std_logic := '0';
+		icSend		: in  std_logic;
+		idDataSend	: in  std_logic_vector(7 downto 0);
+		idParity    : in  std_logic := '0';
+		ocSEmpty	: out std_logic;
+		ocSFull		: out std_logic;
+		ocSAlmostE	: out std_logic;
+		ocSAlmostF	: out std_logic;
+		
+		odTransmit	: out std_logic;
+		
+		odDataRcvd	: out  std_logic_vector(7 downto 0);
+		odParity    : out  std_logic;
+		ocREmpty	: out std_logic;
+		ocRFull		: out std_logic;
+		ocRAlmostE	: out std_logic;
+		ocRAlmostF	: out std_logic;
+		icRReadEn	: in  std_logic;
+		
+		idReceive	: in  std_logic
+	);
+end UART;
+
+architecture arch of UART is
+	
+--  component clkDivider is
+--      generic(
+--          GEN_FreqIn_Hz   : integer := 200000000;
+--          GEN_FreqOut_Hz  : integer := 100000000
+--      );
+--      port ( 
+--          iClk_in         : in  STD_LOGIC;
+--          iReset          : in  STD_LOGIC;
+--          oClk_out        : out STD_LOGIC);
+--  end component;
+	
+	component clkEnable is
+    generic(
+        GEN_FreqIn_Hz   : integer := 200000000; --! signal description input clock frequency in Hz for <iClkIn>
+        GEN_FreqOut_Hz  : integer := 100000000  --! signal description output clock frequency in Hz for <oClkEn>
+    );
+    port ( 
+        iClkin         : in  STD_LOGIC;        --! signal description input clock
+        iReset         : in  STD_LOGIC;        --! signal description synchronous reset (should be tied to '0')
+        oeClkEn        : out STD_LOGIC         --! signal description output clockEnable
+    );
+    end component;
+
+    component clkEnableProgrammable is
+    port (
+        iClkin         : in  STD_LOGIC;        --! input clock
+        iReset         : in  STD_LOGIC;        --! synchronous reset (should be tied to '0')
+        icLimit        : in  integer;        --! programmable limit value for generating the ClkEnable pulse
+        oeClkEn        : out STD_LOGIC         --! output clockEnable
+    );
+    end component clkEnableProgrammable;
+	
+	component SenderAndFifo is
+		port  (
+			iSysClk 	: in  std_logic;
+			ieClkEn     : in  std_logic;
+			ieBaudClkEn	: in  std_logic;	
+			iReset		: in  std_logic;
+			icSend		: in  std_logic;
+			idDataSend	: in  std_logic_vector(7 downto 0);
+			idParity    : in  std_logic;
+			icEnableParity : in std_logic;
+			ocSEmpty	: out std_logic;
+			ocSFull		: out std_logic;
+			ocSAlmostE	: out std_logic;
+			ocSAlmostF	: out std_logic;
+			
+			odTransmit	: out std_logic
+		);
+	end component;
+	
+	component ReceiverAndFifo is
+		port  (
+			iSysClk 	: in  std_logic;
+			ieClkEn     : in  std_logic;
+			ie4xBaudClkEn	: in  std_logic;	
+			iReset		: in  std_logic;
+			
+			odDataRcvd	: out  std_logic_vector(7 downto 0);
+			odParity    : out  std_logic;
+			icEnableParity:in  std_logic;
+			ocREmpty	: out std_logic;
+			ocRFull		: out std_logic;
+			ocRAlmostE	: out std_logic;
+			ocRAlmostF	: out std_logic;
+			icRReadEn	: in  std_logic;
+			
+			idReceive	: in  std_logic
+		);
+	end component;
+	
+	signal seBauDSender		: std_logic;
+	signal se4BaudReceiver  : std_logic;
+
+	signal ExtBLimitx4	: integer;
+		
+begin
+
+
+--  sendDivider : clkDivider 
+--                  GENERIC MAP (
+--                      GEN_FreqIn_Hz   => 4,
+--                      GEN_FreqOut_Hz  => 1
+--                  )
+--                  PORT MAP(
+--                      iClk_in     => i4xBaudClk,
+--                      iReset      => '0',
+--                      oClk_out    => sBAUDSender
+--                  );
+fixedBaudLimit : if GEN_HasExternBaudLimit = false generate	
+	clkEnableSender : clkEnable 
+    generic map(
+        GEN_FreqIn_Hz   => GEN_SysClockinHz,
+        GEN_FreqOut_Hz  => GEN_Baudrate
+    )
+    port map( 
+        iClkin         => iSysClk,
+        iReset         => '0',
+        oeClkEn        => seBauDSender
+    );
+    
+    clkEnableReceiver : clkEnable 
+    generic map(
+        GEN_FreqIn_Hz   => GEN_SysClockinHz,
+        GEN_FreqOut_Hz  => 4 * GEN_Baudrate
+    )
+    port map( 
+        iClkin         => iSysClk,
+        iReset         => '0',
+        oeClkEn        => se4BaudReceiver
+    );
+end generate;
+	
+extBaudLimit :  if GEN_HasExternBaudLimit = true generate
+   clkEnableSender : clkEnableProgrammable
+    port map(
+        iClkin         => iSysClk,
+        iReset         => '0',
+	icLimit	       => icBaudLExt,
+        oeClkEn        => seBauDSender
+    );
+
+    ExtBLimitx4 <= icBaudLExt / 4;
+    clkEnableReceiver : clkEnableProgrammable
+    port map(
+        iClkin         => iSysClk,
+        iReset         => '0',
+	icLimit        => ExtBLimitx4,
+        oeClkEn        => se4BaudReceiver
+    );
+end generate;
+
+	SenderAndFifo1 : SenderAndFifo 
+					PORT MAP (
+						iSysClk 	=> iSysClk,
+						ieClkEn     => ieClkEn,
+						ieBaudClkEn	=> seBAUDSender,
+						iReset		=> iReset,
+						
+						icSend		=> icSend,
+						icEnableParity=> icEnableParity,
+						idDataSend	=> idDataSend,
+						idParity    => idParity,
+						ocSEmpty	=> ocSEmpty,
+						ocSFull		=> ocSFull,
+						ocSAlmostE	=> ocSAlmostE,
+						ocSAlmostF	=> ocSAlmostF,
+						
+						odTransmit	=> odTransmit
+					);
+	
+	ReceiverAndFifo1 : ReceiverAndFifo 
+					PORT MAP (
+						iSysClk 	=> iSysClk,
+						ieClkEn     => ieClkEn,
+						ie4xBaudClkEn	=> se4BaudReceiver,
+						iReset		=> iReset,
+						
+						icEnableParity=>icEnableParity,
+						odDataRcvd	=> odDataRcvd,
+						odParity    => odParity,
+						ocREmpty	=> ocREmpty,
+						ocRFull		=> ocRFull,
+						ocRAlmostE	=> ocRAlmostE,
+						ocRAlmostF	=> ocRAlmostF,
+						icRReadEn	=> icRReadEn,
+						
+						idReceive	=> idReceive
+					);
+	
+end arch;
+