From 4f00cedb90b6dd2097f3ab9a53f669f06719c126 Mon Sep 17 00:00:00 2001 From: Dominik Meyer Date: Sun, 5 Jan 2014 03:14:50 +0100 Subject: [PATCH] ADD: switched to a fork of the used UART --- src/Modules/UART/License | 339 +++++++++++++++++++++ src/Modules/UART/Makefile.files | 3 + src/Modules/UART/README | 8 + src/{ => Modules}/UART/Receiver.vhd | 24 +- src/{ => Modules}/UART/ReceiverAndFifo.vhd | 118 +++---- src/{ => Modules}/UART/Sender.vhd | 23 +- src/{ => Modules}/UART/SenderAndFifo.vhd | 84 +++-- src/{ => Modules}/UART/UART.vhd | 13 +- src/UART/Fifo.vhd | 84 ----- src/UART/FifoS3e.vhd | 78 ----- src/UART/FifoS6.vhd | 79 ----- src/UART/Makefile.files | 14 - 12 files changed, 515 insertions(+), 352 deletions(-) create mode 100644 src/Modules/UART/License create mode 100644 src/Modules/UART/Makefile.files create mode 100644 src/Modules/UART/README rename src/{ => Modules}/UART/Receiver.vhd (81%) rename src/{ => Modules}/UART/ReceiverAndFifo.vhd (53%) rename src/{ => Modules}/UART/Sender.vhd (80%) rename src/{ => Modules}/UART/SenderAndFifo.vhd (71%) rename src/{ => Modules}/UART/UART.vhd (94%) delete mode 100644 src/UART/Fifo.vhd delete mode 100644 src/UART/FifoS3e.vhd delete mode 100644 src/UART/FifoS6.vhd delete mode 100644 src/UART/Makefile.files diff --git a/src/Modules/UART/License b/src/Modules/UART/License new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/src/Modules/UART/License @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/src/Modules/UART/Makefile.files b/src/Modules/UART/Makefile.files new file mode 100644 index 0000000..55a3758 --- /dev/null +++ b/src/Modules/UART/Makefile.files @@ -0,0 +1,3 @@ +VHDL_SRC += Receiver.vhd ReceiverAndFifo.vhd Sender.vhd SenderAndFifo.vhd UART.vhd +VHDL_PKG += +VHDL_TB += diff --git a/src/Modules/UART/README b/src/Modules/UART/README new file mode 100644 index 0000000..80ab205 --- /dev/null +++ b/src/Modules/UART/README @@ -0,0 +1,8 @@ + Uart Component +--------------------- + +Component is a fork of the UART Component written by Marcel Eckert marcel.eckert@hsu-hh.de +at the Helmut Schmidt University in Hamburg. + +The main difference at the moment is the usage of the SimpleFifo Component as Fifos +not multiple Implementations for different FPGAs. \ No newline at end of file diff --git a/src/UART/Receiver.vhd b/src/Modules/UART/Receiver.vhd similarity index 81% rename from src/UART/Receiver.vhd rename to src/Modules/UART/Receiver.vhd index d349d85..f8091d6 100644 --- a/src/UART/Receiver.vhd +++ b/src/Modules/UART/Receiver.vhd @@ -27,15 +27,17 @@ entity Receiver is ie4BaudClkEn : in std_logic;reset : in std_logic; --! signal description asynchronous reset Rx : in STD_LOGIC; --! signal description signal for the RS232 Rx line data : out STD_LOGIC_VECTOR (7 downto 0); --! signal description last data received + parity : out std_logic; --! signal description + icEnableParity: in std_logic; --! signal description Enable reception of the parity bit ready : out STD_LOGIC); --! '0' signals receving in progress, if '1' after a previous '0' signals data available at end Receiver; architecture Behavioral of Receiver is signal z, tz : integer range 0 to 63; signal result, tresult : STD_LOGIC_VECTOR(7 downto 0); - + signal sdParity : std_logic; begin - process (z, Rx) + process (z, Rx, icEnableParity) begin if z = 0 then if (Rx ='0') then @@ -46,7 +48,8 @@ begin elsif z <= 36 then tz <= z + 1; - + elsif (z <= 40 and icEnableParity='1') then + tz <= z+1; else tz <= 0; @@ -55,11 +58,12 @@ begin tresult <= Rx & result(7 downto 1); - process (reset, iSysClk) + process (iSysClk) begin if (iSysClk'event and iSysClk = '1') then if reset = '1' then z <= 0; + sdParity <= '0'; elsif ie4BaudClkEn = '1' then z <= tz; case z is @@ -87,7 +91,14 @@ begin when 33 => result <= tresult; -- D(7) - + + when 37 => + result <= result; + if (icEnableParity='1') then + sdParity <= Rx; + else + sdParity <= '0'; + end if; -- optional TODO: add check for STOP-Bit(s) when others => result <= result; @@ -95,7 +106,8 @@ begin end if; end if; end process; - + + parity <= sdParity; data <= result; ready <= '1' when z = 0 else '0'; diff --git a/src/UART/ReceiverAndFifo.vhd b/src/Modules/UART/ReceiverAndFifo.vhd similarity index 53% rename from src/UART/ReceiverAndFifo.vhd rename to src/Modules/UART/ReceiverAndFifo.vhd index bfc14a4..527e787 100644 --- a/src/UART/ReceiverAndFifo.vhd +++ b/src/Modules/UART/ReceiverAndFifo.vhd @@ -22,20 +22,21 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ReceiverAndFifo is + port ( - iSysClk : in std_logic; --! signal description System side clock - ieClkEn : in std_logic; + iSysClk : in std_logic; --! signal description System side clock + ieClkEn : in std_logic; ie4xBaudClkEn : in std_logic; --! signal description UART clock (4xBAUD Rate frequency!) - iReset : in std_logic; --! signal description asynchronous reset - - odDataRcvd : out std_logic_vector(7 downto 0); --! signal description data from Fifo - ocREmpty : out std_logic; --! signal description indicates that Fifo is empty - ocRFull : out std_logic; --! signal description indicates that Fifo is full - ocRAlmostE : out std_logic; --! signal description indicates that Fifo is empty to half full - ocRAlmostF : out std_logic; --! signal description indicates that Fifo is half full to full - icRReadEn : in std_logic; --! signal description get next value from Fifo (Fifo is in First Word Fall Through Mode!) - - idReceive : in std_logic --! signal description signal for the RS232 Tx line + iReset : in std_logic; --! signal description asynchronous reset + icEnableParity: in std_logic; --! signal description allow reception of parity bit + odDataRcvd : out std_logic_vector(7 downto 0); --! signal description data from Fifo + odParity : out std_logic; --! possible parity bit + ocREmpty : out std_logic; --! signal description indicates that Fifo is empty + ocRFull : out std_logic; --! signal description indicates that Fifo is full + ocRAlmostE : out std_logic; --! signal description indicates that Fifo is empty to half full + ocRAlmostF : out std_logic; --! signal description indicates that Fifo is half full to full + icRReadEn : in std_logic; --! signal description get next value from Fifo (Fifo is in First Word Fall Through Mode!) + idReceive : in std_logic --! signal description signal for the RS232 Tx line ); end ReceiverAndFifo; @@ -43,39 +44,50 @@ architecture arch of ReceiverAndFifo is component Receiver is port ( - iSysClk : in std_logic; - ie4BaudClkEn : in std_logic; - reset : in STD_LOGIC; - Rx : in STD_LOGIC; - data : out STD_LOGIC_VECTOR (7 downto 0); - ready : out STD_LOGIC); + iSysClk : in std_logic; + ie4BaudClkEn : in std_logic; + reset : in STD_LOGIC; + Rx : in STD_LOGIC; + data : out STD_LOGIC_VECTOR (7 downto 0); + parity : out std_logic; + icEnableParity: in std_logic; + ready : out STD_LOGIC); end component; - component Fifo is - port ( - iReset : in std_logic; - - iClkWrite : in std_logic; - icWriteEn : in std_logic; - - iClkRead : in std_logic; - icReadEn : in std_logic; - - idDataIn : in std_logic_vector(7 downto 0); - odDataOut : out std_logic_vector(7 downto 0); - - ocEmpty : out std_logic; - ocFull : out std_logic; - - ocAlmostE : out std_logic; - ocAlmostF : out std_logic - ); - end component; + component SimpleFifo is + generic ( + GEN_WIDTH : integer := 9; --! Data width of each data word + GEN_DEPTH : integer := 256; --! how many values can be stored in Fifo + + GEN_A_EMPTY : integer := 2; --! when is the FIFO signaled as almost empty + GEN_A_FULL : integer := 250 --! when is the FIFO signaled as almost full + + ); + port ( + icReset : in std_logic; + + icWriteClk : in std_logic; + icWe : in std_logic; + + icReadClk : in std_logic; + icReadEnable : in std_logic; + + idData : in std_logic_vector(8 downto 0); + odData : out std_logic_vector(8 downto 0); + + ocEmpty : out std_logic; + ocFull : out std_logic; + + ocAempty : out std_logic; + ocAfull : out std_logic + ); + end component; signal scRWrite : std_logic; signal scRWriteEn : std_logic; signal seRReadEn : std_logic; - signal sdDataRcvd : STD_LOGIC_VECTOR (7 downto 0); + signal sdDataRcvd : STD_LOGIC_VECTOR (8 downto 0); + signal sdParity : std_logic; signal scRcvrEmpty : std_logic; signal scRcvrFull : std_logic; @@ -90,24 +102,25 @@ begin scRWriteEn <= scRWrite and ie4xBaudClkEn; seRReadEn <= icRReadEn and ieClkEn; - rcvFifo : Fifo + rcvFifo : SimpleFifo PORT MAP( - iReset => iReset, + icReset => iReset, - iClkWrite => iSysClk, - icWriteEn => scRWriteEn, + icWriteClk => iSysClk, + icWe => scRWriteEn, - iClkRead => iSysClk, - icReadEn => seRReadEn, + icReadClk => iSysClk, + icReadEnable => seRReadEn, - idDataIn => sdDataRcvd, - odDataOut => odDataRcvd, + idData => sdDataRcvd, + odData(8 downto 1) => odDataRcvd, + odData(0) => odParity, ocEmpty => scRcvrEmpty, ocFull => scRcvrFull, - ocAlmostE => scRcvrAEmpty, - ocAlmostF => scRcvrAFull + ocAempty => scRcvrAEmpty, + ocAfull => scRcvrAFull ); ocREmpty <= scRcvrEmpty; @@ -121,10 +134,13 @@ begin ie4BaudClkEn => ie4xBaudClkEn, reset => iReset, Rx => idReceive, - data => sdDataRcvd, + data => sdDataRcvd(8 downto 1), + parity => sdDataRcvd(0), + icEnableParity => icEnableParity, ready => scReaderReady ); - + + ReceiverCtrl : process (iSysClk) begin if (rising_edge(iSysClk)) then diff --git a/src/UART/Sender.vhd b/src/Modules/UART/Sender.vhd similarity index 80% rename from src/UART/Sender.vhd rename to src/Modules/UART/Sender.vhd index 958ea02..938179d 100644 --- a/src/UART/Sender.vhd +++ b/src/Modules/UART/Sender.vhd @@ -27,15 +27,17 @@ entity Sender is iReset : in STD_LOGIC; --! signal description synchronous reset icSend : in STD_LOGIC; --! signal description force a send of idData : in STD_LOGIC_VECTOR (7 downto 0); --! signal description the data to be sent + idParity : in std_logic; --! signal description the parity bit of the data + icEnableParity:in std_logic; --! signal description enable sending of the parity bit odTransmit : out STD_LOGIC; --! signal description signal for the RS232 Tx line ocReady : out STD_LOGIC; --! signal description signals availability of the Sender (no Sending in Progress) ocSyn : out STD_LOGIC); --! signal description signals sending of first Stop Bit end Sender; architecture Behavioral of Sender is - signal temp, tnext :STD_LOGIC_VECTOR(11 downto 0); + signal temp, tnext :STD_LOGIC_VECTOR(12 downto 0); - type StateType is (WAITING, INIT, HIGH, START, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, STOP1, STOP2); + type StateType is (WAITING, INIT, HIGH, START, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, PARITY, STOP1, STOP2); signal state : StateType; begin process(iSysClk) @@ -53,7 +55,11 @@ begin case state is when WAITING => if (icSend = '1') then - temp <= "11" & idData & "01"; + if (icEnableParity = '1') then + temp <= "11" & idParity & idData & "01"; + else + temp <= "111" & idData & "01"; + end if; state <= INIT; else state <= WAITING; @@ -90,7 +96,14 @@ begin state <= DATA7; when DATA7 => - state <= STOP1; + if (icEnableParity = '1') then + state <= PARITY; + else + state <= STOP1; + end if; + + when PARITY => + state <= STOP1; when STOP1 => state <= STOP2; @@ -104,7 +117,7 @@ begin end if; end process; - tnext <= '1' & temp(11 downto 1); + tnext <= '1' & temp(12 downto 1); ocReady <= '1' when state = WAITING else '0'; diff --git a/src/UART/SenderAndFifo.vhd b/src/Modules/UART/SenderAndFifo.vhd similarity index 71% rename from src/UART/SenderAndFifo.vhd rename to src/Modules/UART/SenderAndFifo.vhd index e3079a5..7d53785 100644 --- a/src/UART/SenderAndFifo.vhd +++ b/src/Modules/UART/SenderAndFifo.vhd @@ -32,6 +32,8 @@ entity SenderAndFifo is icSend : in std_logic; --! signal description add data to Fifo (Enable Signal) idDataSend : in std_logic_vector(7 downto 0); --! signal description data to be added to the Fifo + idParity : in std_logic; --! signal description the parity bit for the data + icEnableParity: in std_logic; --! signal description enable the sending of the parity bit ocSEmpty : out std_logic; --! signal description indicates that Fifo is empty ocSFull : out std_logic; --! signal description indicates that Fifo is full ocSAlmostE : out std_logic; --! signal description indicates that Fifo is empty to half full @@ -49,36 +51,46 @@ architecture arch of SenderAndFifo is iReset : in STD_LOGIC; icSend : in STD_LOGIC; idData : in STD_LOGIC_VECTOR (7 downto 0); + idParity : in std_logic; + icEnableParity:in std_logic; odTransmit : out STD_LOGIC; ocReady : out STD_LOGIC; ocSyn : out STD_LOGIC); end component; - component Fifo is - port ( - iReset : in std_logic; - - iClkWrite : in std_logic; - icWriteEn : in std_logic; - - iClkRead : in std_logic; - icReadEn : in std_logic; - - idDataIn : in std_logic_vector(7 downto 0); - odDataOut : out std_logic_vector(7 downto 0); - - ocEmpty : out std_logic; - ocFull : out std_logic; - - ocAlmostE : out std_logic; - ocAlmostF : out std_logic - ); - end component; + component SimpleFifo is + generic ( + GEN_WIDTH : integer := 9; --! Data width of each data word + GEN_DEPTH : integer := 256; --! how many values can be stored in Fifo + + GEN_A_EMPTY : integer := 2; --! when is the FIFO signaled as almost empty + GEN_A_FULL : integer := 250 --! when is the FIFO signaled as almost full + + ); + port ( + icReset : in std_logic; + + icWriteClk : in std_logic; + icWe : in std_logic; + + icReadClk : in std_logic; + icReadEnable : in std_logic; + + idData : in std_logic_vector(8 downto 0); + odData : out std_logic_vector(8 downto 0); + + ocEmpty : out std_logic; + ocFull : out std_logic; + + ocAempty : out std_logic; + ocAfull : out std_logic + ); + end component; signal scSenderRead : std_logic; signal scSenderReadEn : std_logic; - signal sdDataToSend : STD_LOGIC_VECTOR (7 downto 0); + signal sdDataToSend : STD_LOGIC_VECTOR (8 downto 0); signal scSenderEmpty : std_logic; signal scSenderFull : std_logic; signal scSenderAEmpty : std_logic; @@ -93,31 +105,35 @@ architecture arch of SenderAndFifo is signal seSend : std_logic; + signal sdFifoDataIn : std_logic_vector(8 downto 0); + begin scSenderReadEn <= scSenderRead and ieBaudClkEn; seSend <= icSend and ieClkEn; - sendFifo : Fifo + sendFifo : SimpleFifo PORT MAP( - iReset => iReset, + icReset => iReset, - iClkWrite => iSysClk, - icWriteEn => seSend, + icWriteClk => iSysClk, + icWe => seSend, - iClkRead => iSysClk, - icReadEn => scSenderReadEn, + icReadClk => iSysClk, + icReadEnable => scSenderReadEn, - idDataIn => idDataSend, - odDataOut => sdDataToSend, + idData => sdFifoDataIn, + odData => sdDataToSend, ocEmpty => scSenderEmpty, ocFull => scSenderFull, - ocAlmostE => scSenderAEmpty, - ocAlmostF => scSenderAFull + ocAempty => scSenderAEmpty, + ocAfull => scSenderAFull ); - + + sdFifoDataIn <= idDataSend & idParity; + ocSEmpty <= scSenderEmpty; ocSFull <= scSenderFull; ocSAlmostE <= scSenderAEmpty; @@ -129,7 +145,9 @@ begin ieBaudClkEn => ieBaudClkEn, iReset => iReset, icSend => scSenderSendReq, - idData => sdDataToSend, + idData => sdDataToSend(8 downto 1), + idParity => sdDataToSend(0), + icEnableParity=>icEnableParity, odTransmit => odTransmit, ocReady => scSenderReady, ocSyn => scSyn diff --git a/src/UART/UART.vhd b/src/Modules/UART/UART.vhd similarity index 94% rename from src/UART/UART.vhd rename to src/Modules/UART/UART.vhd index 6979f3a..079604a 100644 --- a/src/UART/UART.vhd +++ b/src/Modules/UART/UART.vhd @@ -29,9 +29,10 @@ entity UART is iReset : in std_logic; icBaudLExt : in integer := 0; - + icEnableParity : in std_logic := '0'; icSend : in std_logic; idDataSend : in std_logic_vector(7 downto 0); + idParity : in std_logic := '0'; ocSEmpty : out std_logic; ocSFull : out std_logic; ocSAlmostE : out std_logic; @@ -40,6 +41,7 @@ entity UART is odTransmit : out std_logic; odDataRcvd : out std_logic_vector(7 downto 0); + odParity : out std_logic; ocREmpty : out std_logic; ocRFull : out std_logic; ocRAlmostE : out std_logic; @@ -90,9 +92,10 @@ architecture arch of UART is ieClkEn : in std_logic; ieBaudClkEn : in std_logic; iReset : in std_logic; - icSend : in std_logic; idDataSend : in std_logic_vector(7 downto 0); + idParity : in std_logic; + icEnableParity : in std_logic; ocSEmpty : out std_logic; ocSFull : out std_logic; ocSAlmostE : out std_logic; @@ -110,6 +113,8 @@ architecture arch of UART is iReset : in std_logic; odDataRcvd : out std_logic_vector(7 downto 0); + odParity : out std_logic; + icEnableParity:in std_logic; ocREmpty : out std_logic; ocRFull : out std_logic; ocRAlmostE : out std_logic; @@ -189,7 +194,9 @@ end generate; iReset => iReset, icSend => icSend, + icEnableParity=> icEnableParity, idDataSend => idDataSend, + idParity => idParity, ocSEmpty => ocSEmpty, ocSFull => ocSFull, ocSAlmostE => ocSAlmostE, @@ -205,7 +212,9 @@ end generate; ie4xBaudClkEn => se4BaudReceiver, iReset => iReset, + icEnableParity=>icEnableParity, odDataRcvd => odDataRcvd, + odParity => odParity, ocREmpty => ocREmpty, ocRFull => ocRFull, ocRAlmostE => ocRAlmostE, diff --git a/src/UART/Fifo.vhd b/src/UART/Fifo.vhd deleted file mode 100644 index 8e0aa19..0000000 --- a/src/UART/Fifo.vhd +++ /dev/null @@ -1,84 +0,0 @@ --------------------------------------------------------------------------------- --- Entity: Fifo --------------------------------------------------------------------------------- --- Copyright ... 2011 --- Filename : Fifo.vhd --- Creation date : 2011-05-27 --- Author(s) : marcel --- Version : 1.00 --- Description : --------------------------------------------------------------------------------- --- File History: --- Date Version Author Comment --- 2011-05-27 1.00 marcel Creation of File --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity Fifo is - port ( - iReset : in std_logic; - - iClkWrite : in std_logic; - icWriteEn : in std_logic; - - iClkRead : in std_logic; - icReadEn : in std_logic; - - idDataIn : in std_logic_vector(7 downto 0); - odDataOut : out std_logic_vector(7 downto 0); - - ocEmpty : out std_logic; - ocFull : out std_logic; - - ocAlmostE : out std_logic; - ocAlmostF : out std_logic - ); -end Fifo; - -architecture arch of Fifo is - signal sdDataOut : std_logic_vector(31 downto 0); - signal sdDataIn : std_logic_vector(31 downto 0); -begin - - FIFO36_inst : FIFO36 - generic map ( - ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold - ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold - DATA_WIDTH => 9, -- Sets data width to 4, 9, 18, or 36 - DO_REG => 1, -- Enable output register ( 0 or 1) - -- Must be 1 if the EN_SYN = FALSE - EN_SYN => FALSE, -- Specified FIFO as Asynchronous (FALSE) or - -- Synchronous (TRUE) - FIRST_WORD_FALL_THROUGH => TRUE, -- Sets the FIFO FWFT to TRUE or FALSE - SIM_MODE => "FAST") -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation - -- Design Guide" for details - port map ( - ALMOSTEMPTY => ocAlmostE, -- 1-bit almost empty output flag - ALMOSTFULL => ocAlmostF, -- 1-bit almost full output flag - DO => sdDataOut, -- 32-bit data output - DOP => open, -- 4-bit parity data output - EMPTY => ocEmpty, -- 1-bit empty output flag - FULL => ocFull, -- 1-bit full output flag - RDCOUNT => open, -- 13-bit read count output - RDERR => open, -- 1-bit read error output - WRCOUNT => open, -- 13-bit write count output - WRERR => open, -- 1-bit write error - DI => sdDataIn, -- 32-bit data input - DIP => "1111", -- 4-bit parity input - RDCLK => iClkRead, -- 1-bit read clock input - RDEN => icReadEn, -- 1-bit read enable input - RST => iReset, -- 1-bit reset input - WRCLK => iClkWrite, -- 1-bit write clock input - WREN => icWriteEn -- 1-bit write enable input - ); - - odDataOut <= sdDataOut(7 downto 0); - sdDataIn <= X"000000" & idDataIn; -end arch; - diff --git a/src/UART/FifoS3e.vhd b/src/UART/FifoS3e.vhd deleted file mode 100644 index 849e109..0000000 --- a/src/UART/FifoS3e.vhd +++ /dev/null @@ -1,78 +0,0 @@ --------------------------------------------------------------------------------- --- Entity: Fifo --------------------------------------------------------------------------------- --- Copyright ... 2011 --- Filename : Fifo.vhd --- Creation date : 2011-05-27 --- Author(s) : marcel --- Version : 1.00 --- Description : --------------------------------------------------------------------------------- --- File History: --- Date Version Author Comment --- 2011-05-27 1.00 marcel Creation of File --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity Fifo is - port ( - iReset : in std_logic; - - iClkWrite : in std_logic; - icWriteEn : in std_logic; - - iClkRead : in std_logic; - icReadEn : in std_logic; - - idDataIn : in std_logic_vector(7 downto 0); - odDataOut : out std_logic_vector(7 downto 0); - - ocEmpty : out std_logic; - ocFull : out std_logic; - - ocAlmostE : out std_logic; - ocAlmostF : out std_logic - ); -end Fifo; - -architecture arch of Fifo is - component fifo_generator_v7_2 - port ( - rst: in std_logic; - wr_clk: in std_logic; - rd_clk: in std_logic; - din: in std_logic_vector(7 downto 0); - wr_en: in std_logic; - rd_en: in std_logic; - dout: out std_logic_vector(7 downto 0); - full: out std_logic; - almost_full: out std_logic; - empty: out std_logic; - almost_empty: out std_logic); - end component; - -begin - - fifo_generator_v7_2_0 : fifo_generator_v7_2 - port map ( - rst => iReset, - wr_clk => iClkWrite, - rd_clk => iClkRead, - din => idDataIn, - wr_en => icWriteEn, - rd_en => icReadEn, - dout => odDataOut, - full => ocFull, - almost_full => ocAlmostF, - empty => ocEmpty, - almost_empty => ocAlmostE - ); - -end arch; - diff --git a/src/UART/FifoS6.vhd b/src/UART/FifoS6.vhd deleted file mode 100644 index 319bb0b..0000000 --- a/src/UART/FifoS6.vhd +++ /dev/null @@ -1,79 +0,0 @@ --------------------------------------------------------------------------------- --- Entity: Fifo --------------------------------------------------------------------------------- --- Copyright ... 2011 --- Filename : Fifo.vhd --- Creation date : 2011-05-27 --- Author(s) : marcel --- Version : 1.00 --- Description : --------------------------------------------------------------------------------- --- File History: --- Date Version Author Comment --- 2011-05-27 1.00 marcel Creation of File --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity Fifo is - port ( - iReset : in std_logic; - - iClkWrite : in std_logic; - icWriteEn : in std_logic; - - iClkRead : in std_logic; - icReadEn : in std_logic; - - idDataIn : in std_logic_vector(7 downto 0); - odDataOut : out std_logic_vector(7 downto 0); - - ocEmpty : out std_logic; - ocFull : out std_logic; - - ocAlmostE : out std_logic; - ocAlmostF : out std_logic - ); -end Fifo; - -architecture arch of Fifo is - component FifoS6 IS - PORT ( - wr_clk : IN STD_LOGIC; - rst : IN STD_LOGIC; - rd_clk : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - wr_en : IN STD_LOGIC; - rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - full : OUT STD_LOGIC; - almost_full : OUT STD_LOGIC; - empty : OUT STD_LOGIC; - almost_empty : OUT STD_LOGIC - ); - END component; - -begin - - FifoS6_0 : FifoS6 - port map ( - rst => iReset, - wr_clk => iClkWrite, - rd_clk => iClkRead, - din => idDataIn, - wr_en => icWriteEn, - rd_en => icReadEn, - dout => odDataOut, - full => ocFull, - almost_full => ocAlmostF, - empty => ocEmpty, - almost_empty => ocAlmostE - ); - -end arch; - diff --git a/src/UART/Makefile.files b/src/UART/Makefile.files deleted file mode 100644 index a9e0473..0000000 --- a/src/UART/Makefile.files +++ /dev/null @@ -1,14 +0,0 @@ -ifeq ($(FPGA_FAMILY),spartan6) - VHDL_SRC += FifoS6.vhd -else -ifeq ($(FPGA_FAMILY),spartan3e) - VHDL_SRC += FifoS3e.vhd -else - VHDL_SRC += Fifo.vhd -endif -endif - - -VHDL_SRC += Receiver.vhd ReceiverAndFifo.vhd Sender.vhd SenderAndFifo.vhd UART.vhd -VHDL_PKG += -VHDL_TB +=