From 2ff599262add176ebe04e00fa27d64c0ef7abc5b Mon Sep 17 00:00:00 2001
From: Dominik Meyer <dmeyer@federationhq.de>
Date: Mon, 30 Dec 2013 14:47:52 +0100
Subject: [PATCH] RM: removed unused components

---
 src/{Steuerwerk.vhd => ControlUnit.vhd} |  0
 src/MemGuard.vhd                        | 46 --------------------
 src/antibeat_device.vhd                 | 56 -------------------------
 3 files changed, 102 deletions(-)
 rename src/{Steuerwerk.vhd => ControlUnit.vhd} (100%)
 delete mode 100644 src/MemGuard.vhd
 delete mode 100644 src/antibeat_device.vhd

diff --git a/src/Steuerwerk.vhd b/src/ControlUnit.vhd
similarity index 100%
rename from src/Steuerwerk.vhd
rename to src/ControlUnit.vhd
diff --git a/src/MemGuard.vhd b/src/MemGuard.vhd
deleted file mode 100644
index a2bff69..0000000
--- a/src/MemGuard.vhd
+++ /dev/null
@@ -1,46 +0,0 @@
--------------------------------------------------------
---! @file 
---! @brief memory guard to only answer for the correct memory space
---! @author Dominik Meyer
---! @email dmeyer@hsu-hh.de
---! @date 2013-07-18
--------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
---! memory guard to only answer for the correct memory space
-
-entity MemGuard is
-    generic (
-        GEN_start   :   std_logic_vector(15 downto 0) := x"0000";
-        GEN_end     :   std_logic_vector(15 downto 0) := x"0004" 
-        
-    );
-    
-    port  (
-        icAddr      :   in  std_logic_vector(15 downto 0);
-        ocEnable    :   out std_logic
-                
-    );
-end MemGuard;
-
-architecture arch of MemGuard is
-
-begin
-    
-    
-    process(icAddr)
-    begin
-        if (icAddr >= GEN_start and icAddr <= GEN_end) then
-            ocEnable <= '1';
-        else
-            ocEnable <= '0';
-        end if;
-    end process;
-    
-end arch;
-
diff --git a/src/antibeat_device.vhd b/src/antibeat_device.vhd
deleted file mode 100644
index 3f48531..0000000
--- a/src/antibeat_device.vhd
+++ /dev/null
@@ -1,56 +0,0 @@
--------------------------------------------------------
---! @file 
---! @brief anti beat device for key buttons on the fpga
---! @author Dominik Meyer
---! @email dmeyer@hsu-hh.de
---! @date 2010-06-22
--------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
---! anti beat device for key buttons on the fpga
-
---! this anti beat device makes sure that button_in is only transmitted to button_output once every second
-entity antibeat_device is
-    port  (
-        button_in   :   in   std_logic;      --! the button input, for example the button from an fpga
-        button_out  :   out  std_logic;      --! the button output, for example going to the reset or clk of a processor
-        counter		:	in	 std_logic_vector(31 downto 0);	--! the number of clk ticks to wait
-        clk         :   in   std_logic;       --! input clock
-        reset		:	in	std_logic
-      );
-end antibeat_device;
-
-architecture arch of antibeat_device is
-    
-begin
-    
-    process(clk,button_in)
-        variable waiting : integer := 0;
-        variable running : boolean := false;
-    begin
-        
-		if (button_in = '1' and running=false) then
-			running:=true;
-			waiting:=0;
-			button_out <= '1';
-		elsif (rising_edge(clk)) then
-			if (running = true) then
-				waiting := waiting + 1;
-			end if;
-			
-			if (waiting> counter and button_in='0') then
-				running := false;
-				button_out <= '0';
-			end if;
-						
-        end if;
-        
-    end process;
-    
-end arch;
-