2013-07-02 22:32:18 +02:00
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-- Entity: UART
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--------------------------------------------------------------------------------
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-- Copyright ... 2011
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-- Filename : UART.vhd
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-- Creation date : 2011-05-27
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-- Author(s) : marcel
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-- Version : 1.00
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-- Description : <short description>
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--------------------------------------------------------------------------------
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-- File History:
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-- Date Version Author Comment
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-- 2011-05-27 1.00 marcel Creation of File
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity UART is
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generic(
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GEN_SysClockinHz : integer := 33000000;
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GEN_Baudrate : integer := 115200; --! Baudrate to use
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GEN_HasExternBaudLimit : boolean := false
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);
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port (
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iSysClk : in std_logic;
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ieClkEn : in std_logic;
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iReset : in std_logic;
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icBaudLExt : in integer := 0;
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2014-01-05 03:14:50 +01:00
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icEnableParity : in std_logic := '0';
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2013-07-02 22:32:18 +02:00
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icSend : in std_logic;
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idDataSend : in std_logic_vector(7 downto 0);
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2014-01-05 03:14:50 +01:00
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idParity : in std_logic := '0';
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2013-07-02 22:32:18 +02:00
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ocSEmpty : out std_logic;
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ocSFull : out std_logic;
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ocSAlmostE : out std_logic;
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ocSAlmostF : out std_logic;
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odTransmit : out std_logic;
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odDataRcvd : out std_logic_vector(7 downto 0);
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2014-01-05 03:14:50 +01:00
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odParity : out std_logic;
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2013-07-02 22:32:18 +02:00
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ocREmpty : out std_logic;
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ocRFull : out std_logic;
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ocRAlmostE : out std_logic;
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ocRAlmostF : out std_logic;
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icRReadEn : in std_logic;
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idReceive : in std_logic
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);
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end UART;
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architecture arch of UART is
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-- component clkDivider is
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-- generic(
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-- GEN_FreqIn_Hz : integer := 200000000;
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-- GEN_FreqOut_Hz : integer := 100000000
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-- );
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-- port (
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-- iClk_in : in STD_LOGIC;
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-- iReset : in STD_LOGIC;
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-- oClk_out : out STD_LOGIC);
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-- end component;
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component clkEnable is
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generic(
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GEN_FreqIn_Hz : integer := 200000000; --! signal description input clock frequency in Hz for <iClkIn>
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GEN_FreqOut_Hz : integer := 100000000 --! signal description output clock frequency in Hz for <oClkEn>
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);
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port (
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iClkin : in STD_LOGIC; --! signal description input clock
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iReset : in STD_LOGIC; --! signal description synchronous reset (should be tied to '0')
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oeClkEn : out STD_LOGIC --! signal description output clockEnable
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);
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end component;
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component clkEnableProgrammable is
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port (
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iClkin : in STD_LOGIC; --! input clock
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iReset : in STD_LOGIC; --! synchronous reset (should be tied to '0')
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icLimit : in integer; --! programmable limit value for generating the ClkEnable pulse
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oeClkEn : out STD_LOGIC --! output clockEnable
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);
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end component clkEnableProgrammable;
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component SenderAndFifo is
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port (
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iSysClk : in std_logic;
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ieClkEn : in std_logic;
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ieBaudClkEn : in std_logic;
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iReset : in std_logic;
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icSend : in std_logic;
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idDataSend : in std_logic_vector(7 downto 0);
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2014-01-05 03:14:50 +01:00
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idParity : in std_logic;
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icEnableParity : in std_logic;
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2013-07-02 22:32:18 +02:00
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ocSEmpty : out std_logic;
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ocSFull : out std_logic;
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ocSAlmostE : out std_logic;
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ocSAlmostF : out std_logic;
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odTransmit : out std_logic
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);
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end component;
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component ReceiverAndFifo is
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port (
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iSysClk : in std_logic;
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ieClkEn : in std_logic;
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ie4xBaudClkEn : in std_logic;
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iReset : in std_logic;
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odDataRcvd : out std_logic_vector(7 downto 0);
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2014-01-05 03:14:50 +01:00
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odParity : out std_logic;
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icEnableParity:in std_logic;
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2013-07-02 22:32:18 +02:00
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ocREmpty : out std_logic;
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ocRFull : out std_logic;
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ocRAlmostE : out std_logic;
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ocRAlmostF : out std_logic;
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icRReadEn : in std_logic;
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idReceive : in std_logic
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);
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end component;
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signal seBauDSender : std_logic;
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signal se4BaudReceiver : std_logic;
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signal ExtBLimitx4 : integer;
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begin
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-- sendDivider : clkDivider
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-- GENERIC MAP (
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-- GEN_FreqIn_Hz => 4,
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-- GEN_FreqOut_Hz => 1
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-- )
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-- PORT MAP(
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-- iClk_in => i4xBaudClk,
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-- iReset => '0',
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-- oClk_out => sBAUDSender
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-- );
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fixedBaudLimit : if GEN_HasExternBaudLimit = false generate
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clkEnableSender : clkEnable
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generic map(
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GEN_FreqIn_Hz => GEN_SysClockinHz,
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GEN_FreqOut_Hz => GEN_Baudrate
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)
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port map(
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iClkin => iSysClk,
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iReset => '0',
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oeClkEn => seBauDSender
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);
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clkEnableReceiver : clkEnable
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generic map(
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GEN_FreqIn_Hz => GEN_SysClockinHz,
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GEN_FreqOut_Hz => 4 * GEN_Baudrate
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)
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port map(
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iClkin => iSysClk,
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iReset => '0',
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oeClkEn => se4BaudReceiver
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);
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end generate;
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extBaudLimit : if GEN_HasExternBaudLimit = true generate
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clkEnableSender : clkEnableProgrammable
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port map(
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iClkin => iSysClk,
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iReset => '0',
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icLimit => icBaudLExt,
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oeClkEn => seBauDSender
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);
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ExtBLimitx4 <= icBaudLExt / 4;
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clkEnableReceiver : clkEnableProgrammable
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port map(
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iClkin => iSysClk,
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iReset => '0',
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icLimit => ExtBLimitx4,
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oeClkEn => se4BaudReceiver
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);
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end generate;
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SenderAndFifo1 : SenderAndFifo
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PORT MAP (
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iSysClk => iSysClk,
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ieClkEn => ieClkEn,
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ieBaudClkEn => seBAUDSender,
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iReset => iReset,
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icSend => icSend,
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2014-01-05 03:14:50 +01:00
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icEnableParity=> icEnableParity,
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2013-07-02 22:32:18 +02:00
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idDataSend => idDataSend,
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idParity => idParity,
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2013-07-02 22:32:18 +02:00
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ocSEmpty => ocSEmpty,
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ocSFull => ocSFull,
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ocSAlmostE => ocSAlmostE,
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ocSAlmostF => ocSAlmostF,
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odTransmit => odTransmit
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);
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ReceiverAndFifo1 : ReceiverAndFifo
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PORT MAP (
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iSysClk => iSysClk,
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ieClkEn => ieClkEn,
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ie4xBaudClkEn => se4BaudReceiver,
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iReset => iReset,
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2014-01-05 03:14:50 +01:00
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icEnableParity=>icEnableParity,
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odDataRcvd => odDataRcvd,
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odParity => odParity,
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2013-07-02 22:32:18 +02:00
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ocREmpty => ocREmpty,
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ocRFull => ocRFull,
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ocRAlmostE => ocRAlmostE,
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ocRAlmostF => ocRAlmostF,
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icRReadEn => icRReadEn,
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idReceive => idReceive
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);
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end arch;
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