47 lines
2.0 KiB
Makefile
47 lines
2.0 KiB
Makefile
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include Make.sources
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CLEAN_FILES+=*.ucf *.ngc *.prj *.xst xst.log *.lso *.xrpt *.srp _xmsgs xst __ngo *.ngd *.bld xlnx_auto*
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CLEAN_FILES+=.config.old _impact* *.log *.bit *.bgn *.drc *.ngr *.pad *.par *.pcf *.ptwx *.unroutes
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CLEAN_FILES+=*.xpi *.map *.mrp *.ngm *.csv *.txt *.xml *.xwbt *.html
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%.prj: $(VHDL_SRC) $(VHDL_PKG) $(VERILOG_SRC)
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@sleep 1
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@echo "**** Creating Xilinx Project file $@****"
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@if [ -e $@ ]; then rm $@; fi
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@$(foreach f,$(VHDL_PKG),echo "vhdl work $f" >> $@ ;)
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@$(foreach f,$(VHDL_SRC),echo "vhdl work $f" >> $@ ;)
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@$(foreach f,$(VERILOG_SRC),echo "verilog work $f" >> $@ ;)
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%.xst: %.prj
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@echo "**** Creating XST file ($@) ****"
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@echo run > $@
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@echo -ifn $(subst .xst,,$(@F)).prj >>$@
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@echo -ifmt mixed >>$@
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@echo -ofn $(subst .xst,,$(@F)) >>$@
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@echo -ofmt NGC >>$@
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@echo -p ${FPGA} >>$@
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@echo -top ${TOP} >>$@
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@echo "$$XST_PARAMS" >>$@
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%.ngc: %.xst %.prj
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@echo "**** Running XST ($@)****"
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@export XILINXD_LICENSE_FILE=$(XILINX_LICENSE);cd $(dir $<); $(XILINX_PATH)/xst -ifn $(<F) $(XILINX_XST) >xst.log;if [ $$? -ne 0 ]; then grep ERROR xst.log; exit 1; else grep "Minimum period" xst.log; fi
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%.ngd: %.ngc $(UCF)
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@echo "**** Running NGDBUILD ****"
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@export XILINXD_LICENSE_FILE=$(XILINX_LICENSE);$(XILINX_PATH)/ngdbuild $(XILINX_NGDBUILD) -aul -sd ${SD} -dd __ngo -uc $(UCF) -p ${FPGA} $< $@ > ngdbuild.log
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%.bgn %.bit %.drc: %.ncd %_map.ncd
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@echo "**** Creating Bitfile $@****"
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@export XILINXD_LICENSE_FILE=$(XILINX_LICENSE); $(XILINX_PATH)/bitgen $(XILINX_BITGEN) -w $< >bitgen.log
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%.ncd %.pad %_pad.csv %_pad.txt %.par %.xpi: %_map.ncd %.pcf
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@echo "**** Place components and Routing Signals ****"
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@export XILINXD_LICENSE_FILE=$(XILINX_LICENSE); $(XILINX_PATH)/par $(XILINX_PAR) -w $< $@ $*.pcf > place.log
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%_map.mrp %_map.ncd %_map.ngm %.pcf: %.ngd
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@echo "**** Mapping components ****"
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@export XILINXD_LICENSE_FILE=$(XILINX_LICENSE);$(XILINX_PATH)/map $(XILINX_MAP) -w -p ${FPGA} -pr b -c 100 -o $*_map.ncd $< $*.pcf >map.log
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