2013-07-02 22:15:26 +02:00
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include .config
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#location of Makefiles
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MAKEFILES_PATH=/home/dmeyer/Programmieren/Make/Makefiles/
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#which FPGA are we synthesizing for ?
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2013-07-02 22:32:18 +02:00
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FPGA=xc5vlx110t-3-ff1136
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2013-07-02 22:15:26 +02:00
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#NR of the FPGA in jtag chain
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DEVICE_NR=5
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SD= NGC/
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#which is the TOP Module of the project ?
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2013-07-02 22:32:18 +02:00
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TOP=SOC
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UCF=UCF/xc5vlx110t-3-ff1136.ucf
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2013-07-02 22:15:26 +02:00
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#is this a partial reconfiguration project
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RECONFIGURATION=0
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#modelsim vcom Flags
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FLAGS = -O0 -rangecheck -check_synthesis +acc=full
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#xilinx license server
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XILINX_LICENSE=2100@192.168.1.5
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#path to Xilinx tools
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XILINX_PATH=/home/Xilinx/14.1/ISE_DS/ISE/bin/lin64/
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#modelsim license server
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MODELSIM_LICENSE=1718@192.168.1.5
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#path to modelsim tools
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MODELSIM_PATH=/home/modeltech/modelsim/linux_x86_64
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# additional parameters for xilinx tools
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XILINX_XST=
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XILINX_NGDBUILD=
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XILINX_MAP=
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XILINX_PAR=
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XILINX_BITGEN=
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# xst file parameters
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define XST_PARAMS
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-netlist_hierarchy as_optimized
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-lc off
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-reduce_control_sets off
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-fsm_extract YES
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-fsm_encoding Auto
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-safe_implementation Yes
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-shreg_extract YES
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-rom_style Auto
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-auto_bram_packing NO
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf YES
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-keep_hierarchy NO
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-max_fanout 100000
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-bufg 32
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-register_duplication YES
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-register_balancing No
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-optimize_primitives NO
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endef
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export XST_PARAMS
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%/blockRAM.o: %/blockRAM.vhd
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@export LM_LICENSE_FILE=$(MODELSIM_LICENSE);$(MODELSIM_PATH)/vcom -ignorevitalerrors -permissive -work work $< | grep -E 'Compiling|Error:|Warning:'
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@touch $@
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include $(MAKEFILES_PATH)/Makefile
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