69 lines
2.1 KiB
VHDL
69 lines
2.1 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library work;
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use work.cpupkg.all;
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entity SOC is -- Testumgebung f<>r Rechner
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port(clk : in std_logic; -- Taktsignal
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clk_man : in std_logic; -- manuelles Taktsignal
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reset : in std_logic; -- Resetsignal
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led : out std_logic_vector(7 downto 0);
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switch : in std_logic_vector(1 downto 0));
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end SOC;
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architecture Struktur of SOC is
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component Rechner is -- Rechner setzt sich aus CPU, RAM und Bus zusammen
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port( clk : in std_logic; -- Taktsignal
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reset : in std_logic; -- Resetsignal
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data_print_1: out DATA;
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data_print_2: out DATA); -- Ausgabe
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end component Rechner;
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component antibeat_device is
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port (
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button_in : in std_logic; --! the button input, for example the button from an fpga
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button_out : out std_logic; --! the button output, for example going to the reset or clk of a processor
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counter : in std_logic_vector(31 downto 0); --! the number of clk ticks to wait
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clk : in std_logic; --! input clock
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reset : in std_logic
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);
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end component antibeat_device;
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signal data_print_1 : std_logic_vector(15 downto 0);
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signal data_print_2 : std_logic_vector(15 downto 0);
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signal sig_entprellt : std_logic;
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signal output : std_logic_vector(15 downto 0);
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signal clk_out : std_logic;
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begin
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-- select what to display on led
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led <= --(others => '1') when reset='1' else
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output(15 downto 8) when switch(0)='1' else
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output(7 downto 0);
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output <= data_print_1 when switch(1) = '0' else
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data_print_2;
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antibeat: antibeat_device
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port map(
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button_in => clk_man,
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button_out => clk_out,
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counter => x"019BFCC0",
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clk => clk,
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reset => reset
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);
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Rechner_0 : Rechner port map(clk => clk_out,
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reset => reset,
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data_print_1=> data_print_1,
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data_print_2=> data_print_2);
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end Struktur;
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