87 lines
2.0 KiB
VHDL
87 lines
2.0 KiB
VHDL
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-------------------------------------------------------
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--! @file
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--! @brief simple RAM for the IIB2 Akkumulator machine
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--! @author Dominik Meyer
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--! @email dmeyer@hsu-hh.de
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--! @date 2010-11-18
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-------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library work;
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use work.cpupkg.all;
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--! simple RAM for the IIB2 Akkumulator machine using word addressing
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entity RAM is
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port (
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iClk : in std_logic;
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iReset : in std_logic;
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bdData : inout DATA; --! connection to databus
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idAddress : in ADDRESS; --! connection to addressbus
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icEnable : in std_logic; --! enable or disable RAM
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icRnotW : in std_logic --! read/write control
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);
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end RAM;
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architecture arch of RAM is
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type MEMORY is ARRAY(0 to 255) of DATA; --! array of data words
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constant Prog1 : MEMORY := ( --! 4k * 16bit of RAM
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0 => B"0011_000000001010", -- loa 10 (n)
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1 => B"1100_000000001000", -- jpz 8
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2 => B"0101_000000001100", -- sub <1>
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3 => B"0010_000000001010", -- sto 10 (n)
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4 => B"0011_000000001011", -- loa 11 (a)
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5 => B"0100_000000001001", -- add <result>
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6 => B"0010_000000001001", -- sto <result>
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7 => B"1110_000000000000", -- jmp 0
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8 => B"1111_000000000000", -- hlt
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9 => B"0000_000000000000", -- result
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10 => B"0000_000000000011", -- n=3
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11 => B"0000_000000000101", -- a=1
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12 => B"0000_000000000001", -- 1
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others => (others => '0')
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);
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signal sRam : MEMORY;
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signal tData : DATA;
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begin
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--! functionality of the RAM
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process(iClk, iReset)
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begin
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if (iReset = '1') then
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sRam <= Prog1;
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tData <= (others => '0');
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elsif (rising_edge(iClk)) then
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if (icRnotW = '0' and icEnable = '1') then
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sRam(conv_integer(unsigned(idAddress))) <= bdData;
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else
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tData <= sRam(conv_integer(unsigned(idAddress)));
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end if;
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end if;
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end process;
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bdData <= tData when icRnotW = '1' else
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(others => 'Z');
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end arch;
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