153 lines
5.5 KiB
BibTeX
153 lines
5.5 KiB
BibTeX
@INPROCEEDINGS{pr:prhmpsoc,
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author={Nguyen, T.D.A. and Kumar, A.},
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booktitle={Field Programmable Logic and Applications (FPL), 2014 24th International Conference on},
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title={PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems},
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year={2014},
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month={Sept},
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pages={1-6},
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keywords={embedded systems;field programmable gate arrays;multiprocessing systems;network-on-chip;reconfigurable architectures;FPGA chip;PR microblaze-hardware accelerators;PR-HMPSoC;bitstream relocation;dynamic FPGA;embedded systems;hardware-software task migration;heterogeneous multiprocessor systems-on-chip;network-on-chip;partially reconfigurable FPGA architectures;powerful computational ability;Clocks;Field programmable gate arrays;Hardware;Loading;Memory management;Program processors;FPGA;bitstream relocation;debug;heterogeneous;multiprocessor;partial reconfiguration;task migration},
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doi={10.1109/FPL.2014.6927492},}
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@article{pr:Gohringer:2014,
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author = {G\"{o}hringer, Diana},
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title = {Reconfigurable Multiprocessor Systems: Handling Hydras Heads -- A Survey},
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journal = {SIGARCH Comput. Archit. News},
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issue_date = {Setember 2014},
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volume = {42},
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number = {4},
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month = dec,
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year = {2014},
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issn = {0163-5964},
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pages = {39--44},
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numpages = {6},
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url = {http://doi.acm.org/10.1145/2693714.2693722},
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doi = {10.1145/2693714.2693722},
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acmid = {2693722},
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publisher = {ACM},
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address = {New York, NY, USA},
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}
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@article{pr:multicore,
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year={2014},
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issn={1018-4864},
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journal={Telecommunication Systems},
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volume={55},
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number={3},
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doi={10.1007/s11235-013-9791-1},
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title={A reconfigurable processor architecture combining multi-core and reconfigurable processing units},
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url={http://dx.doi.org/10.1007/s11235-013-9791-1},
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publisher={Springer US},
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keywords={Multi-core; Dynamic reconfiguration; Processor architecture; Reconfigurable computing},
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author={Yan, Like and Wu, Binbin and Wen, Yuan and Zhang, Shaobin and Chen, Tianzhou},
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pages={333-344},
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language={English}
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}
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@book{koch2012partial,
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title={Partial Reconfiguration on {FPGAs}: Architectures, Tools and Applications},
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author={Koch, Dirk},
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volume={153},
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year={2012},
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publisher={Springer}
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}
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@PhdThesis{pr:prhs,
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author = {M. Eckert},
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title = {{FPGA}-Based System Virtual Machines},
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school = {Helmut-Schmidt-University Hamburg, Germany},
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year = {2014},
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}
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@article{pr:mrp,
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author = {Meyer, Dominik and Klauer, Bernd},
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title = {Multicore reconfiguration platform an alternative to {RAMPSoC}},
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journal = {SIGARCH Comput. Archit. News},
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issue_date = {September 2011},
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volume = {39},
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number = {4},
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month = dec,
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year = {2011},
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issn = {0163-5964},
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pages = {102--103},
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numpages = {2},
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publisher = {ACM},
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address = {New York, NY, USA},
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}
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@phdthesis{pr:mrp2,
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author = {Dominik Meyer},
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title = {Multicore Reconfiguration Platform - A Research and Evaluation
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FPGA Framework for Runtime Reconfigurable Systems},
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school = {Helmut-Schmidt-University Hamburg, Germany},
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year = {2015},
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}
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@article{pr:benefits,
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title={Benefits of partial reconfiguration},
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author={Kao, Cindy},
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journal={Xcell journal},
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volume={55},
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pages={65--67},
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year={2005}
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}
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@Manual{pr:xilinx,
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title = {Partial Reconfiguration User Guide},
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month = {April},
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year = {2013},
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note = {\url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug702.pdf}},
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author = {{Xilinx, Inc.}}
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}
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@INPROCEEDINGS{pr:rampsoc0,
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author={G\"{o}hringer, D. and H\"{u}bner, M. and Schatz, V. and Becker, J.},
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booktitle={Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on}, title={Runtime adaptive multi-processor system-on-chip: RAMPSoC},
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year={2008},
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month=apr,
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volume={},
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number={},
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pages={1 -7},
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keywords={application requirement;high performance computing;reconfigurable hardware;runtime adaptive multiprocessor system-on-chip;electronic design automation;multiprocessing systems;optimising compilers;reconfigurable architectures;system-on-chip;},
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ISSN={1530-2075},}
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@INPROCEEDINGS{pr:rampsoc1,
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author={G\"{o}hringer, D. and H\"{u}bner, M. and Perschke, T. and Becker, J.},
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booktitle={Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on}, title={New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability; the RAMPSoC approach},
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year={2008},
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month= sep,
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volume={},
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number={},
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pages={495 -498},
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keywords={FPGA;RAMPSoC approach;field programmable gate arrays;hardware adaptation;image data processing;multiprocessor hardware architectures;object tracking;field programmable gate arrays;microprocessor chips;reconfigurable architectures;system-on-chip;},
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ISSN={},}
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@InProceedings{pr:Hallmannseder,
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booktitle = {PII Workshop},
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author = {{Daniel} Hallmannseder and {Bernd} Klauer},
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title = {{Compilerunterstützung für die Dynamische Rekonfiguration eines Mikroprozessors}},
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publisher = {Technische Informatik, Helmut-Schmidt-Universität},
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year = {2009},
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address = {Hamburg},
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isbn = {32414234234324}
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}
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@inproceedings{pr:niyonkuru,
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author = {Adronis Niyonkuru and
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Hans Christoph Zeidler},
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title = {Designing a Runtime Reconfigurable Processor for General
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Purpose Applications},
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booktitle = {IPDPS},
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year = {2004},
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bibsource = {DBLP, http://dblp.uni-trier.de}
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}
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@Manual{pr:convey,
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title = {Convey Personality Development Kit Reference Manual},
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year = {2010},
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month = {December},
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note = {\url{http://www.conveycomputer.com}},
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author = {{Convey Computer Corporation}}
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}
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