81 lines
5.3 KiB
BibTeX
81 lines
5.3 KiB
BibTeX
@INPROCEEDINGS{path_delay_measurement,
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author={Ruffoni, M. and Bogliolo, A.},
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booktitle={Signal Propagation on Interconnects, 6th IEEE Workshop on. Proceedings}, title={Direct Measures of Path Delays on Commercial FPGA Chips},
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year={2002},
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month={may},
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volume={},
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number={},
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pages={157 -159},
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keywords={Field programmable gate arrays;Frequency;Inverters;Propagation delay;Ring oscillators;Routing;Semiconductor device measurement;Testing;Timing;Wire;},
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}
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@INPROCEEDINGS{pdm:vdl,
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author={Chan, AH. and Roberts, G.W.},
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booktitle={Test Conference, 2001. Proceedings. International},
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title={A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line},
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year={2001},
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month={},
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pages={858-867},
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keywords={CMOS logic circuits;application specific integrated circuits;calibration;delay lines;electric variables measurement;field programmable gate arrays;integrated circuit testing;logic testing;timing;CMOS process;IC prototype;RTL description;calibration;component-invariant technique;differential nonlinearity timing errors;high-resolution timing measurement device;production test;register transfer level description;test time;vernier delay line technique;Circuit testing;Clocks;Counting circuits;Delay lines;Field programmable gate arrays;Performance evaluation;Phase measurement;Propagation delay;Ring oscillators;Timing jitter},
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}
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@article{pdm:selfmeasurement,
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author = {Wong, Justin S. J. and Sedcole, Pete and Cheung, Peter Y. K.},
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title = {Self-Measurement of Combinatorial Circuit Delays in FPGAs},
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journal = {ACM Trans. Reconfigurable Technol. Syst.},
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issue_date = {June 2009},
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volume = {2},
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number = {2},
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month = jun,
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year = {2009},
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pages = {10:1--10:22},
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articleno = {10},
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numpages = {22},
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acmid = {1534920},
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publisher = {ACM},
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address = {New York, NY, USA},
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keywords = {FPGA, Testing, configuration, delay measurement},
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}
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@INPROCEEDINGS{pdm:ro0,
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author={Stanciu, A and Craciun, A},
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booktitle={Optimization of Electrical and Electronic Equipment (OPTIM), 2014 International Conference on},
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title={Generating an unique identifier for FPGA devices},
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year={2014},
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month={May},
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pages={802-808},
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keywords={BCH codes;error correction codes;error detection codes;field programmable gate arrays;logic design;oscillators;FPGA designs;FPGA devices;FPGA security technique;IP vendor;RO security;building automation;complex factories;control systems;cost reduction;device prototyping;digital circuits;electronic devices;hardware attacks;manufacturing flow;medical apparatus;motor controllers;ring oscillators;security issues;switches;system integrator;Encoding;Field programmable gate arrays;Generators;Hardware;Manufacturing;Ring oscillators},
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}
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@INPROCEEDINGS{pdm:ro1,
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author={Jiliang Zhang and Qiang Wu and Yongqiang Lyu and Qiang Zhou and Yici Cai and Yaping Lin and Gang Qu},
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booktitle={Computer-Aided Design and Computer Graphics (CAD/Graphics), 2013 International Conference on},
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title={Design and Implementation of a Delay-Based PUF for FPGA IP Protection},
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year={2013},
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month={Nov},
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pages={107-114},
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keywords={copy protection;delays;digital rights management;field programmable gate arrays;industrial property;logic design;oscillators;Anderson PUF;FPGA IP protection;RO based PUF;arbiter-based PUF;challenge-response pairs;delay-based PUF;digital rights management;field programmable gate arrays;hard macros;intellectual property;key generation;physical unclonable function;resource overhead;ring oscillator;uncontrollable process variations;Delays;Fabrication;Field programmable gate arrays;Multiplexing;Random access memory;Shift registers;Table lookup;EDA;FPGAs;IP cores;fabrication variation;fingerprint;hardware security;intellectual property (IP) protection;physical unclonable functions (PUFs);watermarking},
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}
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@INPROCEEDINGS{pdm:routing,
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author={Zhua, K. and Yao-Wen Chang and Wong, D. F.},
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booktitle={Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on},
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title={Timing-driven routing for symmetrical-array-based FPGAs},
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year={1998},
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month={Oct},
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pages={628-633},
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keywords={circuit layout CAD;field programmable gate arrays;logic CAD;network routing;timing;FPGA;FPGAs;benchmark circuits;complexity;delay;routing resources;symmetrical-array-based;timing-driven global router;timing-driven routing trees;wirelength;Approximation algorithms;Circuit optimization;Delay;Field programmable gate arrays;Information science;Integrated circuit interconnections;Logic arrays;Routing;Switches;Timing},
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}
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@ARTICLE{pdm:routing1,
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author={Alexander, M.J. and Robins, G.},
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journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
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title={New performance-driven FPGA routing algorithms},
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year={1996},
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month={Dec},
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volume={15},
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number={12},
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pages={1505-1517},
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keywords={VLSI;circuit layout CAD;delays;field programmable gate arrays;integrated circuit design;logic CAD;logic partitioning;network routing;trees (mathematics);FPGA;Steiner algorithms;Steiner tree constructions;Xilinx parts;arborescence algorithms;channel width;optimal source-sink pathlengths;performance bounds;routing algorithms;routing solutions;wirelength;Algorithm design and analysis;Circuit simulation;Computer science;Construction industry;Field programmable gate arrays;Flexible printed circuits;Propagation delay;Routing;Steiner trees;Very large scale integration},
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} |