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@INPROCEEDINGS{pr:prhmpsoc,
author={Nguyen, T.D.A. and Kumar, A.},
booktitle={Field Programmable Logic and Applications (FPL), 2014 24th International Conference on},
title={PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems},
year={2014},
month={Sept},
pages={1-6},
keywords={embedded systems;field programmable gate arrays;multiprocessing systems;network-on-chip;reconfigurable architectures;FPGA chip;PR microblaze-hardware accelerators;PR-HMPSoC;bitstream relocation;dynamic FPGA;embedded systems;hardware-software task migration;heterogeneous multiprocessor systems-on-chip;network-on-chip;partially reconfigurable FPGA architectures;powerful computational ability;Clocks;Field programmable gate arrays;Hardware;Loading;Memory management;Program processors;FPGA;bitstream relocation;debug;heterogeneous;multiprocessor;partial reconfiguration;task migration},
doi={10.1109/FPL.2014.6927492},}
@article{pr:Gohringer:2014,
author = {G\"{o}hringer, Diana},
title = {Reconfigurable Multiprocessor Systems: Handling Hydras Heads -- A Survey},
journal = {SIGARCH Comput. Archit. News},
issue_date = {Setember 2014},
volume = {42},
number = {4},
month = dec,
year = {2014},
issn = {0163-5964},
pages = {39--44},
numpages = {6},
url = {http://doi.acm.org/10.1145/2693714.2693722},
doi = {10.1145/2693714.2693722},
acmid = {2693722},
publisher = {ACM},
address = {New York, NY, USA},
}
@article{pr:multicore,
year={2014},
issn={1018-4864},
journal={Telecommunication Systems},
volume={55},
number={3},
doi={10.1007/s11235-013-9791-1},
title={A reconfigurable processor architecture combining multi-core and reconfigurable processing units},
url={http://dx.doi.org/10.1007/s11235-013-9791-1},
publisher={Springer US},
keywords={Multi-core; Dynamic reconfiguration; Processor architecture; Reconfigurable computing},
author={Yan, Like and Wu, Binbin and Wen, Yuan and Zhang, Shaobin and Chen, Tianzhou},
pages={333-344},
language={English}
}
@book{koch2012partial,
title={Partial Reconfiguration on {FPGAs}: Architectures, Tools and Applications},
author={Koch, Dirk},
volume={153},
year={2012},
publisher={Springer}
}
@PhdThesis{pr:prhs,
author = {M. Eckert},
title = {{FPGA}-Based System Virtual Machines},
school = {Helmut-Schmidt-University Hamburg, Germany},
year = {2014},
}
@article{pr:mrp,
author = {Meyer, Dominik and Klauer, Bernd},
title = {Multicore reconfiguration platform an alternative to {RAMPSoC}},
journal = {SIGARCH Comput. Archit. News},
issue_date = {September 2011},
volume = {39},
number = {4},
month = dec,
year = {2011},
issn = {0163-5964},
pages = {102--103},
numpages = {2},
publisher = {ACM},
address = {New York, NY, USA},
}
@phdthesis{pr:mrp2,
author = {Dominik Meyer},
title = {Multicore Reconfiguration Platform - A Research and Evaluation
FPGA Framework for Runtime Reconfigurable Systems},
school = {Helmut-Schmidt-University Hamburg, Germany},
year = {2015},
}
@article{pr:benefits,
title={Benefits of partial reconfiguration},
author={Kao, Cindy},
journal={Xcell journal},
volume={55},
pages={65--67},
year={2005}
}
@Manual{pr:xilinx,
title = {Partial Reconfiguration User Guide},
month = {April},
year = {2013},
note = {\url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug702.pdf}},
author = {{Xilinx, Inc.}}
}
@INPROCEEDINGS{pr:rampsoc0,
author={G\"{o}hringer, D. and H\"{u}bner, M. and Schatz, V. and Becker, J.},
booktitle={Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on}, title={Runtime adaptive multi-processor system-on-chip: RAMPSoC},
year={2008},
month=apr,
volume={},
number={},
pages={1 -7},
keywords={application requirement;high performance computing;reconfigurable hardware;runtime adaptive multiprocessor system-on-chip;electronic design automation;multiprocessing systems;optimising compilers;reconfigurable architectures;system-on-chip;},
ISSN={1530-2075},}
@INPROCEEDINGS{pr:rampsoc1,
author={G\"{o}hringer, D. and H\"{u}bner, M. and Perschke, T. and Becker, J.},
booktitle={Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on}, title={New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability; the RAMPSoC approach},
year={2008},
month= sep,
volume={},
number={},
pages={495 -498},
keywords={FPGA;RAMPSoC approach;field programmable gate arrays;hardware adaptation;image data processing;multiprocessor hardware architectures;object tracking;field programmable gate arrays;microprocessor chips;reconfigurable architectures;system-on-chip;},
ISSN={},}
@InProceedings{pr:Hallmannseder,
booktitle = {PII Workshop},
author = {{Daniel} Hallmannseder and {Bernd} Klauer},
title = {{Compilerunterstützung für die Dynamische Rekonfiguration eines Mikroprozessors}},
publisher = {Technische Informatik, Helmut-Schmidt-Universität},
year = {2009},
address = {Hamburg},
isbn = {32414234234324}
}
@inproceedings{pr:niyonkuru,
author = {Adronis Niyonkuru and
Hans Christoph Zeidler},
title = {Designing a Runtime Reconfigurable Processor for General
Purpose Applications},
booktitle = {IPDPS},
year = {2004},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@Manual{pr:convey,
title = {Convey Personality Development Kit Reference Manual},
year = {2010},
month = {December},
note = {\url{http://www.conveycomputer.com}},
author = {{Convey Computer Corporation}}
}