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@ -71,3 +71,23 @@ month={Aug},}
@@ -71,3 +71,23 @@ month={Aug},}
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urldate = {2016-01-31}, |
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url = {http://en.wikipedia.org/w/index.php?title=Linux&oldid=597293747}, |
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} |
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@INPROCEEDINGS{os:dyract, |
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author={Vipin, K. and Fahmy, S.A.}, |
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booktitle={Field Programmable Logic and Applications (FPL), 2014 24th International Conference on}, |
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title={DyRACT: A partial reconfiguration enabled accelerator and test platform}, |
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year={2014}, |
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pages={1-7}, |
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keywords={application program interfaces;field programmable gate arrays;peripheral interfaces;API;DyRACT;PCIe interface;PR management logic;PR-enabled FPGA platform;data transfer;field programmable gate arrays;high level functions;partial reconfiguration enabled accelerator;static region;test platform;user modules;Clocks;Data transfer;Field programmable gate arrays;Hardware;Registers;Software;Throughput}, |
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doi={10.1109/FPL.2014.6927507}, |
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month={Sept},} |
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@INPROCEEDINGS{os:riffa20, |
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author={Jacobsen, M. and Kastner, R.}, |
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booktitle={Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on}, |
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title={RIFFA 2.0: A reusable integration framework for FPGA accelerators}, |
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year={2013}, |
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pages={1-8}, |
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keywords={field programmable gate arrays;logic design;synchronisation;C/C++;FPGA accelerated applications;FPGA accelerators;FPGA cores;Java;Linux operating system;PCIe link configurations;Python bindings;RIFFA 2.0;Windows operating system;Xilinx FPGA;acceleration platform;commodity CPU;data transfers;open source;reusable integration framework;synchronization;system bus;Acceleration;Clocks;Field programmable gate arrays;Hardware;Protocols;Software;Workstations}, |
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doi={10.1109/FPL.2013.6645504}, |
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month={Sept},} |
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