title = "ASIP design for multiuser MIMO broadcast precoding",
DOI = "10.1109/EuCNC.2017.7980691",
year = "2017",
booktitle = "2017 European Conference on Networks and Communications (EuCNC)",
pages = "1--4",
author = "Shahabuddin, Shahriar and Silvén, Olli and Juntti, Markku",
abstract = "This paper presents an application-specific instruction-set processor (ASIP) for multiuser multiple-input multiple-output (MU-MIMO) broadcast precoding. The ASIP is designed for a base station (BS) with four antennas to perform user scheduling and precoding. Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP. Several special function units (SFU) are designed to accelerate norm-based greedy user scheduling and minimum-mean square error (MMSE) precoding. We also program zero forcing dirty paper coding (ZF-DPC) to demonstrate the reusability of the ASIP. A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology.",
file = "MOVE: A Framework for High-Performance Processor Design-07980691.pdf:http://blackhole.federationhq.de/wikindxindex.php?action=attachments{\_}ATTACHMENTS{\_}CORE{\&}method=downloadAttachment{\&}id=13{\&}resourceId=37{\&}filename=a5f894ceb4b9d293397e935fd5595bb0b3806eea:pdf"
}
@article{Shahbazi2017,
title = "Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5",
ISSN = "2215-0986",
DOI = "https://doi.org/10.1016/j.jestch.2017.07.002",
journal = "Engineering Science and Technology, an International Journal",
pages = "1308--1317",
author = "Shahbazi, Karim and Eshghi, Mohammad and Mirzaee, Reza Faghih",
abstract = "In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific instructions for the above cryptographic algorithms. The proposed architecture has nine function units and two data buses. It has also two types of 32-bit instruction formats for executing Memory Reference (M.R.), Register Reference (R.R.), and Input/Output Reference (I/O R.) instructions. The maximum achieved frequency is 166.916MHz. The encoded output results of the encryption process of a 128-bit input block are obtained after 122, 146 and 170 clock cycles for AES-128, AES-192, and AES-256, respectively. Moreover, it takes 95 clock cycles to encrypt or decrypt a 64-bit input block by using IDEA. Finally, the MD5 hash algorithm requires 469 clock cycles to generate the coded outputs for a block of 512bits. The performance of the proposed processor is compared to some previous and state-of-the-art implementations in terms of speed, latency, throughput, and flexibility.",
file = "MOVE: A Framework for High-Performance Processor Design-1-s2.0-S2215098617300885-main.pdf:http://blackhole.federationhq.de/wikindxindex.php?action=attachments{\_}ATTACHMENTS{\_}CORE{\&}method=downloadAttachment{\&}id=12{\&}resourceId=36{\&}filename=df4677a0755cfe1d4c8470892cefeac1e4147f43:pdf",
