ADD: ein paar einträge
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timestamp = {Wed, 10 Oct 2012 21:28:55 +0200},
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timestamp = {Wed, 10 Oct 2012 21:28:55 +0200},
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biburl = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-1208-4490},
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biburl = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-1208-4490},
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bibsource = {dblp computer science bibliography, http://dblp.org}
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bibsource = {dblp computer science bibliography, http://dblp.org}
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}
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@incollection{app_fpga_accel,
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year={2015},
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isbn={978-3-319-16213-3},
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booktitle={Applied Reconfigurable Computing},
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volume={9040},
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series={Lecture Notes in Computer Science},
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editor={Sano, Kentaro and Soudris, Dimitrios and Hübner, Michael and Diniz, Pedro C.},
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doi={10.1007/978-3-319-16214-0_34},
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title={A Challenge of Portable and High-Speed FPGA Accelerator},
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url={http://dx.doi.org/10.1007/978-3-319-16214-0_34},
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publisher={Springer International Publishing},
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keywords={FPGA; Accelerator; Portable; High-speed; Sorting},
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author={Usui, Takuma and Kobayashi, Ryohei and Kise, Kenji},
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pages={383-392},
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language={English}
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}
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}
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@ -27,10 +27,11 @@ FPGA Framework for Runtime Reconfigurable Systems},
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language = {eng},
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language = {eng},
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}
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}
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@Unpublished{Meyer1,
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@INPROCEEDINGS{Meyer1,
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author = {Meyer, Dominik and Haase, Jan and Eckert, Marcel and Klauer, Bernd},
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author={Meyer, Dominik and Haase, Jan and Eckert, Marcel and Klauer, Bernd},
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title = {Clock Speed Optimization of Partial Runtime Reconfigurable Systems by Signal Latency Measurement},
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booktitle={Proceedings of the 41st Annual Conference of the IEEE Industrial Electronics Society},
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note = {submitted for publication at the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies},
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title={Clock Speed Optimization of Partial Runtime Reconfigurable Systems by Signal Latency Measurement},
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year = {2015},
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year={2015},
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month = jun
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month={November},
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note = {yet to be published}
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}
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}
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