From 76fd3080af5dbdad555e74aee5aa1075e5600713 Mon Sep 17 00:00:00 2001 From: Dominik Meyer Date: Thu, 23 Oct 2014 21:27:09 +0200 Subject: [PATCH] ADD: changes --- other.bib | 14 +++++++++++++- partial_reconfiguration.bib | 11 +++-------- path_delay.bib | 19 ++++++------------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/other.bib b/other.bib index 1e4841a..640391d 100644 --- a/other.bib +++ b/other.bib @@ -9,6 +9,19 @@ Multicore Environments}, pages = {19-37}, } +@INPROCEEDINGS{HaaseHW102, +author={Hofmann, A. and Waldschmidt, K. and Haase, J.}, +booktitle={Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference +on}, +title={{SDVM} - managing heterogeneity in space and time on +multicore {SoCs}}, +year={2010}, +month={June}, +pages={142-148}, +keywords={Field programmable gate arrays;Hardware;Middleware;Multicore +processing;Software;System-on-a-chip}, +} + @article{biddappaclock, author = {Biddappa, Rohit}, title = {Clock Domain Crossing}, @@ -18,6 +31,5 @@ Multicore Environments}, year = {2005}, pages = {2--8}, numpages = {7}, - url = {http://www.cadence.com/india/newsletters/icon_2005-05.pdf}, publisher = {Cadence}, } \ No newline at end of file diff --git a/partial_reconfiguration.bib b/partial_reconfiguration.bib index 505a313..680e02e 100644 --- a/partial_reconfiguration.bib +++ b/partial_reconfiguration.bib @@ -1,5 +1,5 @@ @book{koch2012partial, - title={Partial Reconfiguration on FPGAs: Architectures, Tools and Applications}, + title={Partial Reconfiguration on {FPGAs}: Architectures, Tools and Applications}, author={Koch, Dirk}, volume={153}, year={2012}, @@ -9,14 +9,14 @@ @PhdThesis{pr:prhs, author = {M.M. Eckert}, -title = {FPGA-Based System Virtual Machines}, +title = {{FPGA}-Based System Virtual Machines}, school = {Helmut-Schmidt-Universität/Universität der Bundeswehr Hamburg}, year = {2014}, } @article{pr:mrp, author = {Meyer, Dominik and Klauer, Bernd}, - title = {Multicore reconfiguration platform an alternative to RAMPSoC}, + title = {Multicore reconfiguration platform an alternative to {RAMPSoC}}, journal = {SIGARCH Comput. Archit. News}, issue_date = {September 2011}, volume = {39}, @@ -26,9 +26,6 @@ year = {2014}, issn = {0163-5964}, pages = {102--103}, numpages = {2}, - url = {http://doi.acm.org/10.1145/2082156.2082185}, - doi = {10.1145/2082156.2082185}, - acmid = {2082185}, publisher = {ACM}, address = {New York, NY, USA}, } @@ -58,7 +55,6 @@ volume={}, number={}, pages={1 -7}, keywords={application requirement;high performance computing;reconfigurable hardware;runtime adaptive multiprocessor system-on-chip;electronic design automation;multiprocessing systems;optimising compilers;reconfigurable architectures;system-on-chip;}, -doi={10.1109/IPDPS.2008.4536503}, ISSN={1530-2075},} @INPROCEEDINGS{pr:rampsoc1, @@ -70,7 +66,6 @@ volume={}, number={}, pages={495 -498}, keywords={FPGA;RAMPSoC approach;field programmable gate arrays;hardware adaptation;image data processing;multiprocessor hardware architectures;object tracking;field programmable gate arrays;microprocessor chips;reconfigurable architectures;system-on-chip;}, -doi={10.1109/FPL.2008.4629992}, ISSN={},} @InProceedings{pr:Hallmannseder, diff --git a/path_delay.bib b/path_delay.bib index 144754c..4f90455 100644 --- a/path_delay.bib +++ b/path_delay.bib @@ -7,8 +7,7 @@ volume={}, number={}, pages={157 -159}, keywords={Field programmable gate arrays;Frequency;Inverters;Propagation delay;Ring oscillators;Routing;Semiconductor device measurement;Testing;Timing;Wire;}, -doi={10.1109/SPI.2002.258304}, -ISSN={},} +} @INPROCEEDINGS{pdm:vdl, author={Chan, AH. and Roberts, G.W.}, @@ -18,8 +17,7 @@ year={2001}, month={}, pages={858-867}, keywords={CMOS logic circuits;application specific integrated circuits;calibration;delay lines;electric variables measurement;field programmable gate arrays;integrated circuit testing;logic testing;timing;CMOS process;IC prototype;RTL description;calibration;component-invariant technique;differential nonlinearity timing errors;high-resolution timing measurement device;production test;register transfer level description;test time;vernier delay line technique;Circuit testing;Clocks;Counting circuits;Delay lines;Field programmable gate arrays;Performance evaluation;Phase measurement;Propagation delay;Ring oscillators;Timing jitter}, -doi={10.1109/TEST.2001.966708}, -ISSN={1089-3539},} +} @article{pdm:selfmeasurement, author = {Wong, Justin S. J. and Sedcole, Pete and Cheung, Peter Y. K.}, @@ -30,12 +28,9 @@ ISSN={1089-3539},} number = {2}, month = jun, year = {2009}, - issn = {1936-7406}, pages = {10:1--10:22}, articleno = {10}, numpages = {22}, - url = {http://doi.acm.org/10.1145/1534916.1534920}, - doi = {10.1145/1534916.1534920}, acmid = {1534920}, publisher = {ACM}, address = {New York, NY, USA}, @@ -50,7 +45,7 @@ year={2014}, month={May}, pages={802-808}, keywords={BCH codes;error correction codes;error detection codes;field programmable gate arrays;logic design;oscillators;FPGA designs;FPGA devices;FPGA security technique;IP vendor;RO security;building automation;complex factories;control systems;cost reduction;device prototyping;digital circuits;electronic devices;hardware attacks;manufacturing flow;medical apparatus;motor controllers;ring oscillators;security issues;switches;system integrator;Encoding;Field programmable gate arrays;Generators;Hardware;Manufacturing;Ring oscillators}, -doi={10.1109/OPTIM.2014.6850952},} +} @INPROCEEDINGS{pdm:ro1, author={Jiliang Zhang and Qiang Wu and Yongqiang Lyu and Qiang Zhou and Yici Cai and Yaping Lin and Gang Qu}, @@ -60,7 +55,7 @@ year={2013}, month={Nov}, pages={107-114}, keywords={copy protection;delays;digital rights management;field programmable gate arrays;industrial property;logic design;oscillators;Anderson PUF;FPGA IP protection;RO based PUF;arbiter-based PUF;challenge-response pairs;delay-based PUF;digital rights management;field programmable gate arrays;hard macros;intellectual property;key generation;physical unclonable function;resource overhead;ring oscillator;uncontrollable process variations;Delays;Fabrication;Field programmable gate arrays;Multiplexing;Random access memory;Shift registers;Table lookup;EDA;FPGAs;IP cores;fabrication variation;fingerprint;hardware security;intellectual property (IP) protection;physical unclonable functions (PUFs);watermarking}, -doi={10.1109/CADGraphics.2013.22},} +} @INPROCEEDINGS{pdm:routing, @@ -71,8 +66,7 @@ year={1998}, month={Oct}, pages={628-633}, keywords={circuit layout CAD;field programmable gate arrays;logic CAD;network routing;timing;FPGA;FPGAs;benchmark circuits;complexity;delay;routing resources;symmetrical-array-based;timing-driven global router;timing-driven routing trees;wirelength;Approximation algorithms;Circuit optimization;Delay;Field programmable gate arrays;Information science;Integrated circuit interconnections;Logic arrays;Routing;Switches;Timing}, -doi={10.1109/ICCD.1998.727132}, -ISSN={1063-6404},} +} @ARTICLE{pdm:routing1, author={Alexander, M.J. and Robins, G.}, @@ -84,5 +78,4 @@ volume={15}, number={12}, pages={1505-1517}, keywords={VLSI;circuit layout CAD;delays;field programmable gate arrays;integrated circuit design;logic CAD;logic partitioning;network routing;trees (mathematics);FPGA;Steiner algorithms;Steiner tree constructions;Xilinx parts;arborescence algorithms;channel width;optimal source-sink pathlengths;performance bounds;routing algorithms;routing solutions;wirelength;Algorithm design and analysis;Circuit simulation;Computer science;Construction industry;Field programmable gate arrays;Flexible printed circuits;Propagation delay;Routing;Steiner trees;Very large scale integration}, -doi={10.1109/43.552083}, -ISSN={0278-0070},} \ No newline at end of file +} \ No newline at end of file